1 /*!
2 * @file apm32e10x_smc.c
3 *
4 * @brief This file provides all the SMC firmware functions
5 *
6 * @version V1.0.2
7 *
8 * @date 2022-12-31
9 *
10 * @attention
11 *
12 * Copyright (C) 2021-2023 Geehy Semiconductor
13 *
14 * You may not use this file except in compliance with the
15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16 *
17 * The program is only for reference, which is distributed in the hope
18 * that it will be useful and instructional for customers to develop
19 * their software. Unless required by applicable law or agreed to in
20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23 * and limitations under the License.
24 */
25
26 #include "apm32e10x_smc.h"
27 #include "apm32e10x_rcm.h"
28
29
30 /** @addtogroup APM32E10x_StdPeriphDriver
31 @{
32 */
33
34 /** @addtogroup SMC_Driver
35 * @brief SMC driver modules
36 @{
37 */
38
39 /** @defgroup SMC_Functions Functions
40 @{
41 */
42
43 /*!
44 * @brief Rest the SMC NOR/SRAM Banks registers
45 *
46 * @param bank: Selects the SMC Bank.
47 * The parameter can be one of following values:
48 * @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1
49 * @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2
50 * @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3
51 * @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4
52 *
53 * @retval None
54 */
SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank)55 void SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank)
56 {
57 if (bank == SMC_BANK1_NORSRAM_1)
58 {
59 SMC_Bank1->CSCTRL1 = 0x000030DB;
60 SMC_Bank1->CSTIM1 = 0x0FFFFFFF;
61 SMC_Bank1E->WRTTIM1 = 0x0FFFFFFF;
62 }
63 else if (bank == SMC_BANK1_NORSRAM_2)
64 {
65 SMC_Bank1->CSCTRL2 = 0x000030D2;
66 SMC_Bank1->CSTIM2 = 0x0FFFFFFF;
67 SMC_Bank1E->WRTTIM2 = 0x0FFFFFFF;
68 }
69 else if (bank == SMC_BANK1_NORSRAM_3)
70 {
71 SMC_Bank1->CSCTRL3 = 0x000030D2;
72 SMC_Bank1->CSTIM3 = 0x0FFFFFFF;
73 SMC_Bank1E->WRTTIM3 = 0x0FFFFFFF;
74 }
75 else if (bank == SMC_BANK1_NORSRAM_4)
76 {
77 SMC_Bank1->CSCTRL4 = 0x000030D2;
78 SMC_Bank1->CSTIM4 = 0x0FFFFFFF;
79 SMC_Bank1E->WRTTIM4 = 0x0FFFFFFF;
80 }
81 }
82
83 /*!
84 * @brief Rest the SMC NAND Banks registers
85 *
86 * @param bank: Selects the SMC Bank.
87 * The parameter can be one of following values:
88 * @arg SMC_BANK2_NAND: SMC Bank2 NAND
89 * @arg SMC_BANK3_NAND: SMC Bank3 NAND
90 *
91 * @retval None
92 */
SMC_ResetNAND(SMC_BANK_NAND_T bank)93 void SMC_ResetNAND(SMC_BANK_NAND_T bank)
94 {
95 if(bank == SMC_BANK2_NAND)
96 {
97 /* Set the SMC_Bank2 registers to their reset values */
98 SMC_Bank2->CTRL2 = 0x00000018;
99 SMC_Bank2->STSINT2 = 0x00000040;
100 SMC_Bank2->CMSTIM2 = 0xFCFCFCFC;
101 SMC_Bank2->AMSTIM2 = 0xFCFCFCFC;
102 }
103 /** SMC_BANK3_NAND */
104 else if (bank == SMC_BANK3_NAND)
105 {
106 /* Set the SMC_Bank3 registers to their reset values */
107 SMC_Bank3->CTRL3 = 0x00000018;
108 SMC_Bank3->STSINT3 = 0x00000040;
109 SMC_Bank3->CMSTIM3 = 0xFCFCFCFC;
110 SMC_Bank3->AMSTIM3 = 0xFCFCFCFC;
111 }
112 }
113
114 /*!
115 * @brief Reset the SMC PCCARD Banks registers
116 *
117 * @param None
118 *
119 * @retval None
120 */
SMC_ResetPCCard(void)121 void SMC_ResetPCCard(void)
122 {
123 /** Set the SMC_Bank4 registers to their reset values */
124 SMC_Bank4->CTRL4 = 0x00000018;
125 SMC_Bank4->STSINT4 = 0x00000040;
126 SMC_Bank4->CMSTIM4 = 0xFCFCFCFC;
127 SMC_Bank4->AMSTIM4 = 0xFCFCFCFC;
128 SMC_Bank4->IOSTIM4 = 0xFCFCFCFC;
129 }
130
131 /*!
132 * @brief Config the SMC NOR/SRAM Banks according to the specified parameters in the smcNORSRAMConfig.
133 *
134 * @param smcNORSRAMConfig: Point to a SMC_NORSRAMConfig_T structure
135 *
136 * @retval None
137 */
SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T * smcNORSRAMConfig)138 void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
139 {
140 if (smcNORSRAMConfig->bank == SMC_BANK1_NORSRAM_1)
141 {
142 SMC_Bank1->CSCTRL1_B.ADMUXEN = smcNORSRAMConfig->dataAddressMux;
143 SMC_Bank1->CSCTRL1_B.MTYPECFG = smcNORSRAMConfig->memoryType;
144 SMC_Bank1->CSCTRL1_B.MDBWIDCFG = smcNORSRAMConfig->memoryDataWidth;
145 SMC_Bank1->CSCTRL1_B.BURSTEN = smcNORSRAMConfig->burstAcceesMode;
146 SMC_Bank1->CSCTRL1_B.WSASYNCEN = smcNORSRAMConfig->asynchronousWait;
147 SMC_Bank1->CSCTRL1_B.WSPOLCFG = smcNORSRAMConfig->waitSignalPolarity;
148 SMC_Bank1->CSCTRL1_B.WRAPBEN = smcNORSRAMConfig->wrapMode;
149 SMC_Bank1->CSCTRL1_B.WTIMCFG = smcNORSRAMConfig->waitSignalActive;
150 SMC_Bank1->CSCTRL1_B.WREN = smcNORSRAMConfig->writeOperation;
151 SMC_Bank1->CSCTRL1_B.WAITEN = smcNORSRAMConfig->waiteSignal;
152 SMC_Bank1->CSCTRL1_B.EXTMODEEN = smcNORSRAMConfig->extendedMode;
153 SMC_Bank1->CSCTRL1_B.WRBURSTEN = smcNORSRAMConfig->writeBurst;
154
155 if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR)
156 {
157 SMC_Bank1->CSCTRL1_B.NORFMACCEN = BIT_SET;
158 }
159
160 SMC_Bank1->CSTIM1_B.ADDRSETCFG = \
161 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
162 SMC_Bank1->CSTIM1_B.ADDRHLDCFG = \
163 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
164 SMC_Bank1->CSTIM1_B.DATASETCFG = \
165 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
166 SMC_Bank1->CSTIM1_B.BUSTURNCFG = \
167 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
168 SMC_Bank1->CSTIM1_B.CLKDIVCFG = \
169 smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
170 SMC_Bank1->CSTIM1_B.DATALATCFG = \
171 smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
172 SMC_Bank1->CSTIM1_B.ASYNCACCCFG = \
173 smcNORSRAMConfig->readWriteTimingStruct->accessMode;
174
175 if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
176 {
177 SMC_Bank1E->WRTTIM1_B.ADDRSETCFG = \
178 smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
179 SMC_Bank1E->WRTTIM1_B.ADDRHLDCFG = \
180 smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
181 SMC_Bank1E->WRTTIM1_B.DATASETCFG = \
182 smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
183 SMC_Bank1E->WRTTIM1_B.BUSTURNCFG = \
184 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
185 SMC_Bank1E->WRTTIM1_B.ASYNCACCCFG = \
186 smcNORSRAMConfig->writeTimingStruct->accessMode;
187 }
188 else
189 {
190 SMC_Bank1E->WRTTIM1 = 0x0FFFFFFF;
191 }
192 }
193 else if (smcNORSRAMConfig->bank == SMC_BANK1_NORSRAM_2)
194 {
195 SMC_Bank1->CSCTRL2_B.ADMUXEN = smcNORSRAMConfig->dataAddressMux;
196 SMC_Bank1->CSCTRL2_B.MTYPECFG = smcNORSRAMConfig->memoryType;
197 SMC_Bank1->CSCTRL2_B.MDBWIDCFG = smcNORSRAMConfig->memoryDataWidth;
198 SMC_Bank1->CSCTRL2_B.BURSTEN = smcNORSRAMConfig->burstAcceesMode;
199 SMC_Bank1->CSCTRL2_B.WSASYNCEN = smcNORSRAMConfig->asynchronousWait;
200 SMC_Bank1->CSCTRL2_B.WSPOLCFG = smcNORSRAMConfig->waitSignalPolarity;
201 SMC_Bank1->CSCTRL2_B.WRAPBEN = smcNORSRAMConfig->wrapMode;
202 SMC_Bank1->CSCTRL2_B.WTIMCFG = smcNORSRAMConfig->waitSignalActive;
203 SMC_Bank1->CSCTRL2_B.WREN = smcNORSRAMConfig->writeOperation;
204 SMC_Bank1->CSCTRL2_B.WAITEN = smcNORSRAMConfig->waiteSignal;
205 SMC_Bank1->CSCTRL2_B.EXTMODEEN = smcNORSRAMConfig->extendedMode;
206 SMC_Bank1->CSCTRL2_B.WRBURSTEN = smcNORSRAMConfig->writeBurst;
207
208 if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR)
209 {
210 SMC_Bank1->CSCTRL2_B.NORFMACCEN = BIT_SET;
211 }
212
213 SMC_Bank1->CSTIM2_B.ADDRSETCFG = \
214 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
215 SMC_Bank1->CSTIM2_B.ADDRHLDCFG = \
216 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
217 SMC_Bank1->CSTIM2_B.DATASETCFG = \
218 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
219 SMC_Bank1->CSTIM2_B.BUSTURNCFG = \
220 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
221 SMC_Bank1->CSTIM2_B.CLKDIVCFG = \
222 smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
223 SMC_Bank1->CSTIM2_B.DATALATCFG = \
224 smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
225 SMC_Bank1->CSTIM2_B.ASYNCACCCFG = \
226 smcNORSRAMConfig->readWriteTimingStruct->accessMode;
227
228 if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
229 {
230 SMC_Bank1E->WRTTIM2_B.ADDRSETCFG = \
231 smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
232 SMC_Bank1E->WRTTIM2_B.ADDRHLDCFG = \
233 smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
234 SMC_Bank1E->WRTTIM2_B.DATASETCFG = \
235 smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
236 SMC_Bank1E->WRTTIM2_B.BUSTURNCFG = \
237 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
238 SMC_Bank1E->WRTTIM2_B.ASYNCACCCFG = \
239 smcNORSRAMConfig->writeTimingStruct->accessMode;
240 }
241 else
242 {
243 SMC_Bank1E->WRTTIM2 = 0x0FFFFFFF;
244 }
245 }
246 else if (smcNORSRAMConfig->bank == SMC_BANK1_NORSRAM_3)
247 {
248 SMC_Bank1->CSCTRL3_B.ADMUXEN = smcNORSRAMConfig->dataAddressMux;
249 SMC_Bank1->CSCTRL3_B.MTYPECFG = smcNORSRAMConfig->memoryType;
250 SMC_Bank1->CSCTRL3_B.MDBWIDCFG = smcNORSRAMConfig->memoryDataWidth;
251 SMC_Bank1->CSCTRL3_B.BURSTEN = smcNORSRAMConfig->burstAcceesMode;
252 SMC_Bank1->CSCTRL3_B.WSASYNCEN = smcNORSRAMConfig->asynchronousWait;
253 SMC_Bank1->CSCTRL3_B.WSPOLCFG = smcNORSRAMConfig->waitSignalPolarity;
254 SMC_Bank1->CSCTRL3_B.WRAPBEN = smcNORSRAMConfig->wrapMode;
255 SMC_Bank1->CSCTRL3_B.WTIMCFG = smcNORSRAMConfig->waitSignalActive;
256 SMC_Bank1->CSCTRL3_B.WREN = smcNORSRAMConfig->writeOperation;
257 SMC_Bank1->CSCTRL3_B.WAITEN = smcNORSRAMConfig->waiteSignal;
258 SMC_Bank1->CSCTRL3_B.EXTMODEEN = smcNORSRAMConfig->extendedMode;
259 SMC_Bank1->CSCTRL3_B.WRBURSTEN = smcNORSRAMConfig->writeBurst;
260
261 if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR)
262 {
263 SMC_Bank1->CSCTRL3_B.NORFMACCEN = BIT_SET;
264 }
265
266 SMC_Bank1->CSTIM3_B.ADDRSETCFG = \
267 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
268 SMC_Bank1->CSTIM3_B.ADDRHLDCFG = \
269 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
270 SMC_Bank1->CSTIM3_B.DATASETCFG = \
271 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
272 SMC_Bank1->CSTIM3_B.BUSTURNCFG = \
273 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
274 SMC_Bank1->CSTIM3_B.CLKDIVCFG = \
275 smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
276 SMC_Bank1->CSTIM3_B.DATALATCFG = \
277 smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
278 SMC_Bank1->CSTIM3_B.ASYNCACCCFG = \
279 smcNORSRAMConfig->readWriteTimingStruct->accessMode;
280
281 if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
282 {
283 SMC_Bank1E->WRTTIM3_B.ADDRSETCFG = \
284 smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
285 SMC_Bank1E->WRTTIM3_B.ADDRHLDCFG = \
286 smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
287 SMC_Bank1E->WRTTIM3_B.DATASETCFG = \
288 smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
289 SMC_Bank1E->WRTTIM3_B.BUSTURNCFG = \
290 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
291 SMC_Bank1E->WRTTIM3_B.ASYNCACCCFG = \
292 smcNORSRAMConfig->writeTimingStruct->accessMode;
293 }
294 else
295 {
296 SMC_Bank1E->WRTTIM3 = 0x0FFFFFFF;
297 }
298 }
299 else if (smcNORSRAMConfig->bank == SMC_BANK1_NORSRAM_4)
300 {
301 SMC_Bank1->CSCTRL4_B.ADMUXEN = smcNORSRAMConfig->dataAddressMux;
302 SMC_Bank1->CSCTRL4_B.MTYPECFG = smcNORSRAMConfig->memoryType;
303 SMC_Bank1->CSCTRL4_B.MDBWIDCFG = smcNORSRAMConfig->memoryDataWidth;
304 SMC_Bank1->CSCTRL4_B.BURSTEN = smcNORSRAMConfig->burstAcceesMode;
305 SMC_Bank1->CSCTRL4_B.WSASYNCEN = smcNORSRAMConfig->asynchronousWait;
306 SMC_Bank1->CSCTRL4_B.WSPOLCFG = smcNORSRAMConfig->waitSignalPolarity;
307 SMC_Bank1->CSCTRL4_B.WRAPBEN = smcNORSRAMConfig->wrapMode;
308 SMC_Bank1->CSCTRL4_B.WTIMCFG = smcNORSRAMConfig->waitSignalActive;
309 SMC_Bank1->CSCTRL4_B.WREN = smcNORSRAMConfig->writeOperation;
310 SMC_Bank1->CSCTRL4_B.WAITEN = smcNORSRAMConfig->waiteSignal;
311 SMC_Bank1->CSCTRL4_B.EXTMODEEN = smcNORSRAMConfig->extendedMode;
312 SMC_Bank1->CSCTRL4_B.WRBURSTEN = smcNORSRAMConfig->writeBurst;
313
314 if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR)
315 {
316 SMC_Bank1->CSCTRL4_B.NORFMACCEN = BIT_SET;
317 }
318
319 SMC_Bank1->CSTIM4_B.ADDRSETCFG = \
320 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
321 SMC_Bank1->CSTIM4_B.ADDRHLDCFG = \
322 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
323 SMC_Bank1->CSTIM4_B.DATASETCFG = \
324 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
325 SMC_Bank1->CSTIM4_B.BUSTURNCFG = \
326 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
327 SMC_Bank1->CSTIM4_B.CLKDIVCFG = \
328 smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
329 SMC_Bank1->CSTIM4_B.DATALATCFG = \
330 smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
331 SMC_Bank1->CSTIM4_B.ASYNCACCCFG = \
332 smcNORSRAMConfig->readWriteTimingStruct->accessMode;
333
334 if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
335 {
336 SMC_Bank1E->WRTTIM4_B.ADDRSETCFG = \
337 smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
338 SMC_Bank1E->WRTTIM4_B.ADDRHLDCFG = \
339 smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
340 SMC_Bank1E->WRTTIM4_B.DATASETCFG = \
341 smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
342 SMC_Bank1E->WRTTIM4_B.BUSTURNCFG = \
343 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
344 SMC_Bank1E->WRTTIM4_B.ASYNCACCCFG = \
345 smcNORSRAMConfig->writeTimingStruct->accessMode;
346 }
347 else
348 {
349 SMC_Bank1E->WRTTIM4 = 0x0FFFFFFF;
350 }
351 }
352 }
353
354 /*!
355 * @brief Config the SMC NAND Banks according to the specified parameters in the smcNANDConfig.
356 *
357 * @param smcNANDConfig : Point to a SMC_NANDConfig_T structure.
358 *
359 * @retval None
360 */
SMC_ConfigNAND(SMC_NANDConfig_T * smcNANDConfig)361 void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig)
362 {
363 if (smcNANDConfig->bank == SMC_BANK2_NAND)
364 {
365 SMC_Bank2->CTRL2_B.WAITFEN = smcNANDConfig->waitFeature;
366 SMC_Bank2->CTRL2_B.DBWIDCFG = smcNANDConfig->memoryDataWidth;
367 SMC_Bank2->CTRL2_B.ECCEN = smcNANDConfig->ECC;
368 SMC_Bank2->CTRL2_B.ECCPSCFG = smcNANDConfig->ECCPageSize;
369 SMC_Bank2->CTRL2_B.C2RDCFG = smcNANDConfig->TCLRSetupTime;
370 SMC_Bank2->CTRL2_B.A2RDCFG = smcNANDConfig->TARSetupTime;
371 SMC_Bank2->CTRL2_B.MTYPECFG = BIT_SET;
372
373 SMC_Bank2->CMSTIM2_B.SET2 = \
374 smcNANDConfig->commonSpaceTimingStruct->setupTime;
375 SMC_Bank2->CMSTIM2_B.WAIT2 = \
376 smcNANDConfig->commonSpaceTimingStruct->waitSetupTime;
377 SMC_Bank2->CMSTIM2_B.HLD2 = \
378 smcNANDConfig->commonSpaceTimingStruct->holdSetupTime;
379 SMC_Bank2->CMSTIM2_B.HIZ2 = \
380 smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime;
381
382 SMC_Bank2->AMSTIM2_B.SET2 = \
383 smcNANDConfig->attributeSpaceTimingStruct->setupTime;
384 SMC_Bank2->AMSTIM2_B.WAIT2 = \
385 smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime;
386 SMC_Bank2->AMSTIM2_B.HLD2 = \
387 smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime;
388 SMC_Bank2->AMSTIM2_B.HIZ2 = \
389 smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime;
390 }
391 else if (smcNANDConfig->bank == SMC_BANK3_NAND)
392 {
393 SMC_Bank3->CTRL3_B.WAITFEN = smcNANDConfig->waitFeature;
394 SMC_Bank3->CTRL3_B.DBWIDCFG = smcNANDConfig->memoryDataWidth;
395 SMC_Bank3->CTRL3_B.ECCEN = smcNANDConfig->ECC;
396 SMC_Bank3->CTRL3_B.ECCPSCFG = smcNANDConfig->ECCPageSize;
397 SMC_Bank3->CTRL3_B.C2RDCFG = smcNANDConfig->TCLRSetupTime;
398 SMC_Bank3->CTRL3_B.A2RDCFG = smcNANDConfig->TARSetupTime;
399 SMC_Bank3->CTRL3_B.MTYPECFG = BIT_SET;
400
401 SMC_Bank3->CMSTIM3_B.SET3 = \
402 smcNANDConfig->commonSpaceTimingStruct->setupTime;
403 SMC_Bank3->CMSTIM3_B.WAIT3 = \
404 smcNANDConfig->commonSpaceTimingStruct->waitSetupTime;
405 SMC_Bank3->CMSTIM3_B.HLD3 = \
406 smcNANDConfig->commonSpaceTimingStruct->holdSetupTime;
407 SMC_Bank3->CMSTIM3_B.HIZ3 = \
408 smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime;
409
410 SMC_Bank3->AMSTIM3_B.SET3 = \
411 smcNANDConfig->attributeSpaceTimingStruct->setupTime;
412 SMC_Bank3->AMSTIM3_B.WAIT3 = \
413 smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime;
414 SMC_Bank3->AMSTIM3_B.HLD3 = \
415 smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime;
416 SMC_Bank3->AMSTIM3_B.HIZ3 = \
417 smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime;
418 }
419 }
420
421 /*!
422 * @brief Config the SMC PCCARD according to the specified parameters in the smcPCCardConfig.
423 *
424 * @param smcPCCardConfig: Point to a SMC_PCCARDConfig_T structure.
425 *
426 * @retval None
427 */
SMC_ConfigPCCard(SMC_PCCARDConfig_T * smcPCCardConfig)428 void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig)
429 {
430 SMC_Bank4->CTRL4_B.WAITFEN = smcPCCardConfig->waitFeature;
431 SMC_Bank4->CTRL4_B.C2RDCFG = smcPCCardConfig->TCLRSetupTime;
432 SMC_Bank4->CTRL4_B.A2RDCFG = smcPCCardConfig->TARSetupTime;
433 SMC_Bank4->CTRL4_B.DBWIDCFG = BIT_SET;
434
435 SMC_Bank4->CMSTIM4_B.SET4 = \
436 smcPCCardConfig->commonSpaceTimingStruct->setupTime;
437 SMC_Bank4->CMSTIM4_B.WAIT4 = \
438 smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime;
439 SMC_Bank4->CMSTIM4_B.HLD4 = \
440 smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime;
441 SMC_Bank4->CMSTIM4_B.HIZ4 = \
442 smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime;
443
444 SMC_Bank4->AMSTIM4_B.SET4 = \
445 smcPCCardConfig->attributeSpaceTimingStruct->setupTime;
446 SMC_Bank4->AMSTIM4_B.WAIT4 = \
447 smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime;
448 SMC_Bank4->AMSTIM4_B.HLD4 = \
449 smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime;
450 SMC_Bank4->AMSTIM4_B.HIZ4 = \
451 smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime;
452
453 SMC_Bank4->IOSTIM4_B.SET = \
454 smcPCCardConfig->IOSpaceTimingStruct->setupTime;
455 SMC_Bank4->IOSTIM4_B.WAIT = \
456 smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime;
457 SMC_Bank4->IOSTIM4_B.HLD = \
458 smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime;
459 SMC_Bank4->IOSTIM4_B.HIZ = \
460 smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime;
461 }
462
463 /*!
464 * @brief Fills each smcNORSRAMConfig member with its default value.
465 *
466 * @param smcNORSRAMConfig : Point to a SMC_NORSRAMConfig_T structure.
467 *
468 * @retval None
469 */
SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T * smcNORSRAMConfig)470 void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
471 {
472 /* Reset NOR/SRAM Init structure parameters values */
473 smcNORSRAMConfig->bank = SMC_BANK1_NORSRAM_1;
474 smcNORSRAMConfig->dataAddressMux = SMC_DATA_ADDRESS_MUX_ENABLE;
475 smcNORSRAMConfig->memoryType = SMC_MEMORY_TYPE_SRAM;
476 smcNORSRAMConfig->memoryDataWidth = SMC_MEMORY_DATA_WIDTH_8BIT;
477 smcNORSRAMConfig->burstAcceesMode = SMC_BURST_ACCESS_MODE_DISABLE;
478 smcNORSRAMConfig->asynchronousWait = SMC_ASYNCHRONOUS_WAIT_DISABLE;
479 smcNORSRAMConfig->waitSignalPolarity = SMC_WAIT_SIGNAL_POLARITY_LOW;
480 smcNORSRAMConfig->wrapMode = SMC_WRAP_MODE_DISABLE;
481 smcNORSRAMConfig->waitSignalActive = SMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT_STATE;
482 smcNORSRAMConfig->writeOperation = SMC_WRITE_OPERATION_ENABLE;
483 smcNORSRAMConfig->waiteSignal = SMC_WAITE_SIGNAL_ENABLE;
484 smcNORSRAMConfig->extendedMode = SMC_EXTENDEN_MODE_DISABLE;
485 smcNORSRAMConfig->writeBurst = SMC_WRITE_BURST_DISABLE;
486 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime = 0xF;
487 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime = 0xF;
488 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime = 0xFF;
489 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime = 0xF;
490 smcNORSRAMConfig->readWriteTimingStruct->clockDivision = 0xF;
491 smcNORSRAMConfig->readWriteTimingStruct->dataLatency = 0xF;
492 smcNORSRAMConfig->readWriteTimingStruct->accessMode = SMC_ACCESS_MODE_A;
493 smcNORSRAMConfig->writeTimingStruct->addressSetupTime = 0xF;
494 smcNORSRAMConfig->writeTimingStruct->addressHodeTime = 0xF;
495 smcNORSRAMConfig->writeTimingStruct->dataSetupTime = 0xFF;
496 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime = 0xF;
497 smcNORSRAMConfig->writeTimingStruct->clockDivision = 0xF;
498 smcNORSRAMConfig->writeTimingStruct->dataLatency = 0xF;
499 smcNORSRAMConfig->writeTimingStruct->accessMode = SMC_ACCESS_MODE_A;
500
501 }
502
503 /*!
504 * @brief Fills each smcNANDConfig member with its default value.
505 *
506 * @param smcNANDConfig : Point to a SMC_NANDConfig_T structure.
507 *
508 * @retval None
509 */
SMC_ConfigNANDStructInit(SMC_NANDConfig_T * smcNANDConfig)510 void SMC_ConfigNANDStructInit(SMC_NANDConfig_T* smcNANDConfig)
511 {
512 /* Reset NAND Init structure parameters values */
513 smcNANDConfig->bank = SMC_BANK2_NAND;
514 smcNANDConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE;
515 smcNANDConfig->memoryDataWidth = SMC_MEMORY_DATA_WIDTH_8BIT;
516 smcNANDConfig->ECC = SMC_ECC_DISABLE;
517 smcNANDConfig->ECCPageSize = SMC_ECC_PAGE_SIZE_BYTE_256;
518 smcNANDConfig->TCLRSetupTime = 0x0;
519 smcNANDConfig->TARSetupTime = 0x0;
520 smcNANDConfig->commonSpaceTimingStruct->setupTime = 0xFC;
521 smcNANDConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
522 smcNANDConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
523 smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
524 smcNANDConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
525 smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
526 smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
527 smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
528 }
529
530 /*!
531 * @brief Fills each smcPCCardConfig member with its default value.
532 *
533 * @param smcPCCardConfig : Point to a SMC_PCCARDConfig_T structure.
534 *
535 * @retval None
536 */
SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T * smcPCCardConfig)537 void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T* smcPCCardConfig)
538 {
539 /* Reset PCCARD Init structure parameters values */
540 smcPCCardConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE;
541 smcPCCardConfig->TCLRSetupTime = 0x0;
542 smcPCCardConfig->TARSetupTime = 0x0;
543 smcPCCardConfig->commonSpaceTimingStruct->setupTime = 0xFC;
544 smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
545 smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
546 smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
547 smcPCCardConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
548 smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
549 smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
550 smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
551 smcPCCardConfig->IOSpaceTimingStruct->setupTime = 0xFC;
552 smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime = 0xFC;
553 smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime = 0xFC;
554 smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime = 0xFC;
555 }
556
557 /*!
558 * @brief Enables the specified NOR/SRAM Memory Bank.
559 *
560 * @param bank: Selects the SMC Bank.
561 * The parameter can be one of following values:
562 * @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1
563 * @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2
564 * @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3
565 * @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4
566 *
567 * @retval None
568 */
SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank)569 void SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank)
570 {
571 if (bank == SMC_BANK1_NORSRAM_1)
572 {
573 SMC_Bank1->CSCTRL1_B.MBKEN = BIT_SET;
574 }
575 else if (bank == SMC_BANK1_NORSRAM_2)
576 {
577 SMC_Bank1->CSCTRL2_B.MBKEN = BIT_SET;
578 }
579 else if (bank == SMC_BANK1_NORSRAM_3)
580 {
581 SMC_Bank1->CSCTRL3_B.MBKEN = BIT_SET;
582 }
583 else if (bank == SMC_BANK1_NORSRAM_4)
584 {
585 SMC_Bank1->CSCTRL4_B.MBKEN = BIT_SET;
586 }
587 }
588
589 /*!
590 * @brief Disbles the specified NOR/SRAM Memory Bank.
591 *
592 * @param bank: Selects the SMC Bank.
593 * The parameter can be one of following values:
594 * @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1
595 * @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2
596 * @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3
597 * @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4
598 *
599 * @retval None
600 */
SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank)601 void SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank)
602 {
603 if (bank == SMC_BANK1_NORSRAM_1)
604 {
605 SMC_Bank1->CSCTRL1_B.MBKEN = BIT_RESET;
606 }
607 else if (bank == SMC_BANK1_NORSRAM_2)
608 {
609 SMC_Bank1->CSCTRL2_B.MBKEN = BIT_RESET;
610 }
611 else if (bank == SMC_BANK1_NORSRAM_3)
612 {
613 SMC_Bank1->CSCTRL3_B.MBKEN = BIT_RESET;
614 }
615 else if (bank == SMC_BANK1_NORSRAM_4)
616 {
617 SMC_Bank1->CSCTRL4_B.MBKEN = BIT_RESET;
618 }
619 }
620 /*!
621 * @brief Enables the specified NAND Memory Bank.
622 *
623 * @param bank: Selects the SMC Bank.
624 * The parameter can be one of following values:
625 * @arg SMC_BANK2_NAND: SMC Bank2 NAND
626 * @arg SMC_BANK3_NAND: SMC Bank3 NAND
627 *
628 * @retval None
629 */
SMC_EnableNAND(SMC_BANK_NAND_T bank)630 void SMC_EnableNAND(SMC_BANK_NAND_T bank)
631 {
632 if(bank == SMC_BANK2_NAND)
633 {
634 SMC_Bank2->CTRL2_B.MBKEN = BIT_SET;
635 }
636 else if (bank == SMC_BANK3_NAND)
637 {
638 SMC_Bank3->CTRL3_B.MBKEN = BIT_SET;
639 }
640 }
641
642 /*!
643 * @brief Disbles the specified NAND Memory Bank.
644 *
645 * @param bank: Selects the SMC Bank.
646 * The parameter can be one of following values:
647 * @arg SMC_BANK2_NAND: SMC Bank2 NAND
648 * @arg SMC_BANK3_NAND: SMC Bank3 NAND
649 *
650 * @retval None
651 */
SMC_DisableNAND(SMC_BANK_NAND_T bank)652 void SMC_DisableNAND(SMC_BANK_NAND_T bank)
653 {
654 if(bank == SMC_BANK2_NAND)
655 {
656 SMC_Bank2->CTRL2_B.MBKEN = BIT_RESET;
657 }
658 else if (bank == SMC_BANK3_NAND)
659 {
660 SMC_Bank3->CTRL3_B.MBKEN = BIT_RESET;
661 }
662 }
663
664 /*!
665 * @brief Enables the specified PC Card Memory Bank.
666 *
667 * @param None
668 *
669 * @retval None
670 */
SMC_EnablePCCARD(void)671 void SMC_EnablePCCARD(void)
672 {
673 SMC_Bank4->CTRL4_B.MBKEN = BIT_SET;
674 }
675
676 /*!
677 * @brief Disables the specified PC Card Memory Bank.
678 *
679 * @param None
680 *
681 * @retval None
682 */
SMC_DisablePCCARD(void)683 void SMC_DisablePCCARD(void)
684 {
685 SMC_Bank4->CTRL4_B.MBKEN = BIT_RESET;
686 }
687
688 /*!
689 * @brief Enbles the SMC NAND ECC feature.
690 *
691 * @param bank: Selects the SMC Bank.
692 * The parameter can be one of following values:
693 * @arg SMC_BANK2_NAND: SMC Bank2 NAND
694 * @arg SMC_BANK3_NAND: SMC Bank3 NAND
695 *
696 * @retval None
697 */
SMC_EnableNANDECC(SMC_BANK_NAND_T bank)698 void SMC_EnableNANDECC(SMC_BANK_NAND_T bank)
699 {
700 if (bank == SMC_BANK2_NAND)
701 {
702 SMC_Bank2->CTRL2_B.ECCEN = BIT_SET;
703 }
704 else if (bank == SMC_BANK3_NAND)
705 {
706 SMC_Bank3->CTRL3_B.ECCEN = BIT_SET;
707 }
708 }
709
710 /*!
711 * @brief Disbles or disables the SMC NAND ECC feature.
712 *
713 * @param bank: Selects the SMC Bank.
714 * The parameter can be one of following values:
715 * @arg SMC_BANK2_NAND: SMC Bank2 NAND
716 * @arg SMC_BANK3_NAND: SMC Bank3 NAND
717 *
718 * @retval None
719 *
720 * @note
721 */
SMC_DisableNANDECC(SMC_BANK_NAND_T bank)722 void SMC_DisableNANDECC(SMC_BANK_NAND_T bank)
723 {
724 if (bank == SMC_BANK2_NAND)
725 {
726 SMC_Bank2->CTRL2_B.ECCEN = BIT_RESET;
727 }
728 else if (bank == SMC_BANK3_NAND)
729 {
730 SMC_Bank3->CTRL3_B.ECCEN = BIT_RESET;
731 }
732 }
733
734 /*!
735 * @brief Read the error correction code register value.
736 *
737 * @param bank: Selects the SMC Bank.
738 * The parameter can be one of following values:
739 * @arg SMC_BANK2_NAND: SMC Bank2 NAND
740 * @arg SMC_BANK3_NAND: SMC Bank3 NAND
741 *
742 * @retval The value of Error Correction Code (ECC).
743 */
SMC_ReadECC(SMC_BANK_NAND_T bank)744 uint32_t SMC_ReadECC(SMC_BANK_NAND_T bank)
745 {
746 uint32_t eccval = 0x00000000;
747
748 if(bank == SMC_BANK2_NAND)
749 {
750 eccval = SMC_Bank2->ECCRS2;
751 }
752 else if (bank == SMC_BANK3_NAND)
753 {
754 eccval = SMC_Bank3->ECCRS3;
755 }
756 return eccval;
757 }
758
759 /*!
760 * @brief Enables the specified SMC interrupts.
761 *
762 * @param bank: Selects the SMC Bank.
763 * The parameter can be one of following values:
764 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
765 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
766 * @arg SMC_BANK4_PCCARD: SMC Bank4 PCCARD
767 *
768 * @param interrupt: Select the SMC interrupt sources.
769 * This parameter can be any combination of the following values:
770 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
771 * @arg SMC_INT_LEVEL_HIGH : High level detection interrupt.
772 * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
773 *
774 * @retval None
775 */
SMC_EnableInterrupt(SMC_BANK_NAND_T bank,uint32_t interrupt)776 void SMC_EnableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt)
777 {
778 if(bank == SMC_BANK2_NAND)
779 {
780 SMC_Bank2->STSINT2 |= interrupt;
781 }
782 else if(bank == SMC_BANK3_NAND)
783 {
784 SMC_Bank3->STSINT3 |= interrupt;
785 }
786 else
787 {
788 SMC_Bank4->STSINT4 |= interrupt;
789 }
790 }
791
792 /*!
793 * @brief Enables the specified SMC interrupts.
794 *
795 * @param bank: Selects the SMC Bank.
796 * The parameter can be one of following values:
797 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
798 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
799 * @arg SMC_BANK4_PCCARD: SMC Bank4 PCCARD
800 *
801 * @param interrupt: Select the SMC interrupt sources.
802 * This parameter can be any combination of the following values:
803 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
804 * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt.
805 * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
806 *
807 * @retval None
808 */
SMC_DisableInterrupt(SMC_BANK_NAND_T bank,uint32_t interrupt)809 void SMC_DisableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt)
810 {
811 if(bank == SMC_BANK2_NAND)
812 {
813 SMC_Bank2->STSINT2 &= ~interrupt;
814 }
815 else if(bank == SMC_BANK3_NAND)
816 {
817 SMC_Bank3->STSINT3 &= ~interrupt;
818 }
819 else
820 {
821 SMC_Bank4->STSINT4 &= ~interrupt;
822 }
823 }
824
825 /*!
826 * @brief Read the status of specified SMC flag.
827 *
828 * @param bank: Selects the SMC Bank.
829 * The parameter can be one of following values:
830 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
831 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
832 * @arg SMC_BANK4_PCCARD: SMC Bank4 PCCARD
833 *
834 * @param flag: Select the SMC interrupt sources.
835 * This parameter can be one of the following values:
836 * @arg SMC_FLAG_EDGE_RISING : Rising egde detection Flag.
837 * @arg SMC_FLAG_LEVEL_HIGH : High level detection Flag.
838 * @arg SMC_FLAG_EDGE_FALLING: Falling egde detection Flag.
839 * @arg SMC_FLAG_FIFO_EMPTY : FIFO empty Flag.
840 *
841 * @retval SET or RESET
842 *
843 * @note
844 */
SMC_ReadStatusFlag(SMC_BANK_NAND_T bank,SMC_FLAG_T flag)845 uint16_t SMC_ReadStatusFlag(SMC_BANK_NAND_T bank, SMC_FLAG_T flag)
846 {
847 if (bank == SMC_BANK2_NAND)
848 {
849 return (SMC_Bank2->STSINT2 & flag) ? SET : RESET;
850 }
851 else if (bank == SMC_BANK3_NAND)
852 {
853 return (SMC_Bank3->STSINT3 & flag) ? SET : RESET;
854 }
855 else
856 {
857 return (SMC_Bank4->STSINT4 & flag) ? SET : RESET;
858 }
859 }
860
861 /*!
862 * @brief Clears the SMC's pending flags.
863 *
864 * @param bank: Selects the SMC Bank.
865 * The parameter can be one of following values:
866 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
867 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
868 * @arg SMC_BANK4_PCCARD: SMC Bank4 PCCARD
869 *
870 * @param flag: Select the SMC interrupt sources.
871 * This parameter can be any combination of the following values:
872 * @arg SMC_FLAG_EDGE_RISING : Rising egde detection Flag.
873 * @arg SMC_FLAG_LEVEL_HIGH : High level detection Flag.
874 * @arg SMC_FLAG_EDGE_FALLING: Falling egde detection Flag.
875 *
876 * @retval None
877 */
SMC_ClearStatusFlag(SMC_BANK_NAND_T bank,uint32_t flag)878 void SMC_ClearStatusFlag(SMC_BANK_NAND_T bank, uint32_t flag)
879 {
880 if(bank == SMC_BANK2_NAND)
881 {
882 SMC_Bank2->STSINT2 &= ~flag;
883 }
884 else if(bank == SMC_BANK3_NAND)
885 {
886 SMC_Bank3->STSINT3 &= ~flag;
887 }
888 else
889 {
890 SMC_Bank4->STSINT4 &= ~flag;
891 }
892 }
893
894 /*!
895 * @brief Read the specified SMC interrupt has occurred or not.
896 *
897 * @param bank: Selects the SMC Bank.
898 * The parameter can be one of following values:
899 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
900 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
901 * @arg SMC_BANK4_PCCARD: SMC Bank4 PCCARD
902 *
903 * @param interrupt: Select the SMC interrupt source.
904 * This parameter can be one of the following values:
905 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
906 * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt.
907 * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
908 *
909 * @retval The status of specified SMC interrupt source.
910 */
SMC_ReadIntFlag(SMC_BANK_NAND_T bank,SMC_INT_T flag)911 uint16_t SMC_ReadIntFlag(SMC_BANK_NAND_T bank, SMC_INT_T flag)
912 {
913 uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
914
915 if(bank == SMC_BANK2_NAND)
916 {
917 tmpsr = SMC_Bank2->STSINT2;
918 }
919 else if(bank == SMC_BANK3_NAND)
920 {
921 tmpsr = SMC_Bank3->STSINT3;
922 }
923 else
924 {
925 tmpsr = SMC_Bank4->STSINT4;
926 }
927
928 itstatus = tmpsr & flag;
929 itenable = tmpsr & (flag >> 3);
930
931 if((itstatus != RESET) && (itenable != RESET))
932 {
933 return SET;
934 }
935 else
936 {
937 return RESET;
938 }
939 }
940
941 /*!
942 * @brief Clears the SMC's interrupt Flag.
943 *
944 * @param bank: Selects the SMC Bank.
945 * The parameter can be one of following values:
946 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
947 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
948 * @arg SMC_BANK4_PCCARD: SMC Bank4 PCCARD
949 *
950 * @param interrupt: Select the SMC interrupt sources.
951 * This parameter can be any combination of the following values:
952 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
953 * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt.
954 * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
955 *
956 * @retval None
957 */
SMC_ClearIntFlag(SMC_BANK_NAND_T bank,uint32_t flag)958 void SMC_ClearIntFlag(SMC_BANK_NAND_T bank, uint32_t flag)
959 {
960 if(bank == SMC_BANK2_NAND)
961 {
962 SMC_Bank2->STSINT2 &= ~(flag >> 3);
963 }
964 else if(bank == SMC_BANK3_NAND)
965 {
966 SMC_Bank3->STSINT3 &= ~(flag >> 3);
967 }
968 else
969 {
970 SMC_Bank4->STSINT4 &= ~(flag >> 3);
971 }
972 }
973
974 /**@} end of group SMC_Functions */
975 /**@} end of group SMC_Driver */
976 /**@} end of group APM32E10x_StdPeriphDriver */
977