1 /*!
2  * @file       apm32e10x_tmr.h
3  *
4  * @brief      This file contains all the functions prototypes for the TMR firmware library.
5  *
6  * @version     V1.0.2
7  *
8  * @date        2022-12-31
9  *
10  * @attention
11  *
12  *  Copyright (C) 2021-2023 Geehy Semiconductor
13  *
14  *  You may not use this file except in compliance with the
15  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16  *
17  *  The program is only for reference, which is distributed in the hope
18  *  that it will be useful and instructional for customers to develop
19  *  their software. Unless required by applicable law or agreed to in
20  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23  *  and limitations under the License.
24  */
25 
26 /* Define to prevent recursive inclusion */
27 #ifndef __APM32E10X_TMR_H
28 #define __APM32E10X_TMR_H
29 
30 /* Includes */
31 #include "apm32e10x.h"
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 /** @addtogroup APM32E10x_StdPeriphDriver
38   @{
39 */
40 
41 /** @addtogroup TMR_Driver
42   @{
43 */
44 
45 /** @defgroup TMR_Enumerations Enumerations
46   @{
47 */
48 
49 /**
50  * @brief TMR Counter Mode
51  */
52 typedef enum
53 {
54     TMR_COUNTER_MODE_UP             = 0x0000,
55     TMR_COUNTER_MODE_DOWN           = 0x0010,
56     TMR_COUNTER_MODE_CENTERALIGNED1 = 0x0020,
57     TMR_COUNTER_MODE_CENTERALIGNED2 = 0x0040,
58     TMR_COUNTER_MODE_CENTERALIGNED3 = 0x0060
59 } TMR_COUNTER_MODE_T;
60 
61 /**
62  * @brief TMR Clock division
63  */
64 typedef enum
65 {
66     TMR_CLOCK_DIV_1,
67     TMR_CLOCK_DIV_2,
68     TMR_CLOCK_DIV_4
69 } TMR_CLOCK_DIV_T;
70 
71 /**
72  * @brief TMR Output Compare and PWM modes
73  */
74 typedef enum
75 {
76     TMR_OC_MODE_TMRING     = 0x00,
77     TMR_OC_MODE_ACTIVE     = 0x01,
78     TMR_OC_MODE_INACTIVE   = 0x02,
79     TMR_OC_MODE_TOGGEL     = 0x03,
80     TMR_OC_MODE_LOWLEVEL   = 0x04,
81     TMR_OC_MODE_HIGHLEVEL  = 0x05,
82     TMR_OC_MODE_PWM1       = 0x06,
83     TMR_OC_MODE_PWM2       = 0x07
84 } TMR_OC_MODE_T;
85 
86 /**
87  * @brief TMR Output Compare state
88  */
89 typedef enum
90 {
91     TMR_OC_STATE_DISABLE,
92     TMR_OC_STATE_ENABLE
93 } TMR_OC_STATE_T;
94 
95 /**
96  * @brief TMR Output Compare N state
97  */
98 typedef enum
99 {
100     TMR_OC_NSTATE_DISABLE,
101     TMR_OC_NSTATE_ENABLE
102 } TMR_OC_NSTATE_T;
103 
104 /**
105  * @brief TMR Output Compare Polarity
106  */
107 typedef enum
108 {
109     TMR_OC_POLARITY_HIGH,
110     TMR_OC_POLARITY_LOW
111 } TMR_OC_POLARITY_T;
112 
113 /**
114  * @brief TMR Output Compare N Polarity
115  */
116 typedef enum
117 {
118     TMR_OC_NPOLARITY_HIGH,
119     TMR_OC_NPOLARITY_LOW
120 } TMR_OC_NPOLARITY_T;
121 
122 /**
123  * @brief TMR Output Compare Idle State
124  */
125 typedef enum
126 {
127     TMR_OC_IDLE_STATE_RESET,
128     TMR_OC_IDLE_STATE_SET
129 } TMR_OC_IDLE_STATE_T;
130 
131 /**
132  * @brief TMR Output Compare N Idle State
133  */
134 typedef enum
135 {
136     TMR_OC_NIDLE_STATE_RESET,
137     TMR_OC_NIDLE_STATE_SET
138 } TMR_OC_NIDLE_STATE_T;
139 
140 /**
141  * @brief TMR Input Capture Init structure definition
142  */
143 typedef enum
144 {
145     TMR_CHANNEL_1 = 0x0000,
146     TMR_CHANNEL_2 = 0x0004,
147     TMR_CHANNEL_3 = 0x0008,
148     TMR_CHANNEL_4 = 0x000C
149 } TMR_CHANNEL_T;
150 
151 /**
152  * @brief TMR Input Capture Polarity
153  */
154 typedef enum
155 {
156     TMR_IC_POLARITY_RISING   = 0x00,
157     TMR_IC_POLARITY_FALLING  = 0x02,
158     TMR_IC_POLARITY_BOTHEDGE = 0x0A
159 } TMR_IC_POLARITY_T;
160 
161 /**
162  * @brief TMR Input Capture Selection
163  */
164 typedef enum
165 {
166     TMR_IC_SELECTION_DIRECT_TI   = 0x01,
167     TMR_IC_SELECTION_INDIRECT_TI = 0x02,
168     TMR_IC_SELECTION_TRC         = 0x03
169 } TMR_IC_SELECTION_T;
170 
171 /**
172  * @brief TMR Input Capture Prescaler
173  */
174 typedef enum
175 {
176     TMR_IC_PSC_1,
177     TMR_IC_PSC_2,
178     TMR_IC_PSC_4,
179     TMR_IC_PSC_8
180 } TMR_IC_PSC_T;
181 
182 /**
183  * @brief TMR Specifies the Off-State selection used in Run mode
184  */
185 typedef enum
186 {
187     TMR_RMOS_STATE_DISABLE,
188     TMR_RMOS_STATE_ENABLE
189 } TMR_RMOS_STATE_T;
190 
191 /**
192  * @brief TMR Closed state configuration in idle mode
193  */
194 typedef enum
195 {
196     TMR_IMOS_STATE_DISABLE,
197     TMR_IMOS_STATE_ENABLE
198 } TMR_IMOS_STATE_T;
199 
200 /**
201  * @brief TMR Protect mode configuration values
202  */
203 typedef enum
204 {
205     TMR_LOCK_LEVEL_OFF,
206     TMR_LOCK_LEVEL_1,
207     TMR_LOCK_LEVEL_2,
208     TMR_LOCK_LEVEL_3
209 } TMR_LOCK_LEVEL_T;
210 
211 /**
212  * @brief TMR BRK state
213  */
214 typedef enum
215 {
216     TMR_BRK_STATE_DISABLE,
217     TMR_BRK_STATE_ENABLE
218 } TMR_BRK_STATE_T;
219 
220 /**
221  * @brief TMR Specifies the Break Input pin polarity.
222  */
223 typedef enum
224 {
225     TMR_BRK_POLARITY_LOW,
226     TMR_BRK_POLARITY_HIGH
227 } TMR_BRK_POLARITY_T;
228 
229 /**
230  * @brief TMR Specifies the Break Input pin polarity.
231  */
232 typedef enum
233 {
234     TMR_AUTOMATIC_OUTPUT_DISABLE,
235     TMR_AUTOMATIC_OUTPUT_ENABLE
236 } TMR_AUTOMATIC_OUTPUT_T;
237 
238 /**
239  * @brief    TMR_interrupt_sources
240  */
241 typedef enum
242 {
243     TMR_INT_UPDATE = 0x0001,
244     TMR_INT_CC1    = 0x0002,
245     TMR_INT_CC2    = 0x0004,
246     TMR_INT_CC3    = 0x0008,
247     TMR_INT_CC4    = 0x0010,
248     TMR_INT_COM    = 0x0020,
249     TMR_INT_TRG    = 0x0040,
250     TMR_INT_BRK    = 0x0080
251 } TMR_INT_T;
252 
253 /**
254  * @brief    TMR event sources
255  */
256 typedef enum
257 {
258     TMR_EVENT_UPDATE = 0x001,
259     TMR_EVENT_CC1    = 0x002,
260     TMR_EVENT_CC2    = 0x004,
261     TMR_EVENT_CC3    = 0x008,
262     TMR_EVENT_CC4    = 0x010,
263     TMR_EVENT_COM    = 0x020,
264     TMR_EVENT_TRG    = 0x040,
265     TMR_EVENT_BRK    = 0x080
266 } TMR_EVENT_T;
267 
268 /**
269  * @brief    TMR DMA Base Address
270  */
271 typedef enum
272 {
273     TMR_DMA_BASE_CTRL1   = 0x0000,
274     TMR_DMA_BASE_CTRL2   = 0x0001,
275     TMR_DMA_BASE_SMCTRL  = 0x0002,
276     TMR_DMA_BASE_DIEN    = 0x0003,
277     TMR_DMA_BASE_STS     = 0x0004,
278     TMR_DMA_BASE_CEG     = 0x0005,
279     TMR_DMA_BASE_CCM1    = 0x0006,
280     TMR_DMA_BASE_CCM2    = 0x0007,
281     TMR_DMA_BASE_CCEN    = 0x0008,
282     TMR_DMA_BASE_CNT     = 0x0009,
283     TMR_DMA_BASE_PSC     = 0x000A,
284     TMR_DMA_BASE_AUTORLD = 0x000B,
285     TMR_DMA_BASE_REPCNT  = 0x000C,
286     TMR_DMA_BASE_CC1     = 0x000D,
287     TMR_DMA_BASE_CC2     = 0x000E,
288     TMR_DMA_BASE_CC3     = 0x000F,
289     TMR_DMA_BASE_CC4     = 0x0010,
290     TMR_DMA_BASE_BDT     = 0x0011,
291     TMR_DMA_BASE_DCTRL   = 0x0012
292 } TMR_DMA_BASE_T;
293 
294 /**
295  * @brief    TMR DMA Burst Length
296  */
297 typedef enum
298 {
299     TMR_DMA_BURSTLENGTH_1TRANSFER   = 0x0000,
300     TMR_DMA_BURSTLENGTH_2TRANSFERS  = 0x0100,
301     TMR_DMA_BURSTLENGTH_3TRANSFERS  = 0x0200,
302     TMR_DMA_BURSTLENGTH_4TRANSFERS  = 0x0300,
303     TMR_DMA_BURSTLENGTH_5TRANSFERS  = 0x0400,
304     TMR_DMA_BURSTLENGTH_6TRANSFERS  = 0x0500,
305     TMR_DMA_BURSTLENGTH_7TRANSFERS  = 0x0600,
306     TMR_DMA_BURSTLENGTH_8TRANSFERS  = 0x0700,
307     TMR_DMA_BURSTLENGTH_9TRANSFERS  = 0x0800,
308     TMR_DMA_BURSTLENGTH_10TRANSFERS = 0x0900,
309     TMR_DMA_BURSTLENGTH_11TRANSFERS = 0x0A00,
310     TMR_DMA_BURSTLENGTH_12TRANSFERS = 0x0B00,
311     TMR_DMA_BURSTLENGTH_13TRANSFERS = 0x0C00,
312     TMR_DMA_BURSTLENGTH_14TRANSFERS = 0x0D00,
313     TMR_DMA_BURSTLENGTH_15TRANSFERS = 0x0E00,
314     TMR_DMA_BURSTLENGTH_16TRANSFERS = 0x0F00,
315     TMR_DMA_BURSTLENGTH_17TRANSFERS = 0x1000,
316     TMR_DMA_BURSTLENGTH_18TRANSFERS = 0x1100
317 } TMR_DMA_BURSTLENGTH_T;
318 
319 /**
320  * @brief    TMR DMA Soueces
321  */
322 typedef enum
323 {
324     TMR_DMA_SOURCE_UPDATE    = 0x0100,
325     TMR_DMA_SOURCE_CC1       = 0x0200,
326     TMR_DMA_SOURCE_CC2       = 0x0400,
327     TMR_DMA_SOURCE_CC3       = 0x0800,
328     TMR_DMA_SOURCE_CC4       = 0x1000,
329     TMR_DMA_SOURCE_COM       = 0x2000,
330     TMR_DMA_SOURCE_TRG       = 0x4000
331 } TMR_DMA_SOURCE_T;
332 
333 /**
334  * @brief    TMR Internal Trigger Selection
335  */
336 typedef enum
337 {
338     TMR_TRIGGER_SOURCE_ITR0     = 0x00,
339     TMR_TRIGGER_SOURCE_ITR1     = 0x01,
340     TMR_TRIGGER_SOURCE_ITR2     = 0x02,
341     TMR_TRIGGER_SOURCE_ITR3     = 0x03,
342     TMR_TRIGGER_SOURCE_TI1F_ED  = 0x04,
343     TMR_TRIGGER_SOURCE_TI1FP1   = 0x05,
344     TMR_TRIGGER_SOURCE_TI2FP2   = 0x06,
345     TMR_TRIGGER_SOURCE_ETRF     = 0x07
346 } TMR_TRIGGER_SOURCE_T;
347 
348 /**
349  * @brief    TMR  The external Trigger Prescaler.
350  */
351 typedef enum
352 {
353     TMR_EXTTRG_PSC_OFF   = 0x00,
354     TMR_EXTTRG_PSC_DIV2  = 0x01,
355     TMR_EXTTRG_PSC_DIV4  = 0x02,
356     TMR_EXTTRG_PSC_DIV8  = 0x03
357 } TMR_EXTTRG_PSC_T;
358 
359 /**
360  * @brief    TMR External Trigger Polarity
361  */
362 typedef enum
363 {
364     TMR_EXTTGR_POL_NONINVERTED,
365     TMR_EXTTRG_POL_INVERTED
366 } TMR_EXTTRG_POL_T;
367 
368 /**
369  * @brief    TMR Prescaler Reload Mode
370  */
371 typedef enum
372 {
373     TMR_PSC_RELOAD_UPDATE,
374     TMR_PSC_RELOAD_IMMEDIATE
375 } TMR_PSC_RELOAD_T;
376 
377 /**
378  * @brief    TMR Encoder Mode
379  */
380 typedef enum
381 {
382     TMR_ENCODER_MODE_TI1      = 0x01,
383     TMR_ENCODER_MODE_TI2      = 0x02,
384     TMR_ENCODER_MODE_TI12     = 0x03
385 } TMR_ENCODER_MODE_T;
386 
387 /**
388  * @brief    TMR Forced Action
389  */
390 typedef enum
391 {
392     TMR_FORCED_ACTION_INACTIVE = 0x04,
393     TMR_FORCED_ACTION_ACTIVE   = 0x05
394 } TMR_FORCED_ACTION_T;
395 
396 /**
397  * @brief    TMR Output Compare Preload State
398  */
399 typedef enum
400 {
401     TMR_OC_PRELOAD_DISABLE,
402     TMR_OC_PRELOAD_ENABLE
403 } TMR_OC_PRELOAD_T;
404 
405 /**
406  * @brief    TMR Output Compare Preload State
407  */
408 typedef enum
409 {
410     TMR_OC_FAST_DISABLE,
411     TMR_OC_FAST_ENABLE
412 } TMR_OC_FAST_T;
413 
414 /**
415  * @brief    TMR Output Compare Preload State
416  */
417 typedef enum
418 {
419     TMR_OC_CLEAR_DISABLE,
420     TMR_OC_CLEAR_ENABLE
421 } TMR_OC_CLEAR_T;
422 
423 /**
424  * @brief    TMR UpdateSource
425  */
426 typedef enum
427 {
428     TMR_UPDATE_SOURCE_GLOBAL,
429     TMR_UPDATE_SOURCE_REGULAR
430 } TMR_UPDATE_SOURCE_T;
431 
432 /**
433  * @brief    TMR Single Pulse Mode
434  */
435 typedef enum
436 {
437     TMR_SPM_REPETITIVE,
438     TMR_SPM_SINGLE
439 } TMR_SPM_T;
440 
441 /**
442  * @brief    TMR Trigger Output Source
443  */
444 typedef enum
445 {
446     TMR_TRGO_SOURCE_RESET,
447     TMR_TRGO_SOURCE_ENABLE,
448     TMR_TRGO_SOURCE_UPDATE,
449     TMR_TRGO_SOURCE_OC1,
450     TMR_TRGO_SOURCE_OC1REF,
451     TMR_TRGO_SOURCE_OC2REF,
452     TMR_TRGO_SOURCE_OC3REF,
453     TMR_TRGO_SOURCE_OC4REF
454 } TMR_TRGO_SOURCE_T;
455 
456 /**
457  * @brief    TMR Slave Mode
458  */
459 typedef enum
460 {
461     TMR_SLAVE_MODE_RESET     = 0x04,
462     TMR_SLAVE_MODE_GATED     = 0x05,
463     TMR_SLAVE_MODE_TRIGGER   = 0x06,
464     TMR_SLAVE_MODE_EXTERNAL1 = 0x07
465 } TMR_SLAVE_MODE_T;
466 
467 /**
468  * @brief    TMR Flag
469  */
470 typedef enum
471 {
472     TMR_FLAG_UPDATE  = 0x0001,
473     TMR_FLAG_CC1     = 0x0002,
474     TMR_FLAG_CC2     = 0x0004,
475     TMR_FLAG_CC3     = 0x0008,
476     TMR_FLAG_CC4     = 0x0010,
477     TMR_FLAG_COM     = 0x0020,
478     TMR_FLAG_TRG     = 0x0040,
479     TMR_FLAG_BRK     = 0x0080,
480     TMR_FLAG_CC1RC   = 0x0200,
481     TMR_FLAG_CC2RC   = 0x0400,
482     TMR_FLAG_CC3RC   = 0x0800,
483     TMR_FLAG_CC4RC   = 0x1000
484 } TMR_FLAG_T;
485 
486 /**@} end of group TMR_Enumerations */
487 
488 /** @defgroup TMR_Structures Structures
489   @{
490 */
491 
492 /**
493  * @brief    TMR Config struct definition
494  */
495 typedef struct
496 {
497     TMR_COUNTER_MODE_T     countMode;
498     TMR_CLOCK_DIV_T        clockDivision;
499     uint16_t               period;            /*!< This must between 0x0000 and 0xFFFF */
500     uint16_t               division;          /*!< This must between 0x0000 and 0xFFFF */
501     uint8_t                repetitionCounter; /*!< This must between 0x00 and 0xFF, only for TMR1 and TMR8. */
502 } TMR_BaseConfig_T; ;
503 
504 /**
505  * @brief    TMR Config struct definition
506  */
507 typedef struct
508 {
509     TMR_OC_MODE_T          mode;
510     TMR_OC_STATE_T         outputState;
511     TMR_OC_NSTATE_T        outputNState;
512     TMR_OC_POLARITY_T      polarity;
513     TMR_OC_NPOLARITY_T     nPolarity;
514     TMR_OC_IDLE_STATE_T    idleState;
515     TMR_OC_NIDLE_STATE_T   nIdleState;
516     uint16_t               pulse;     /*!< This must between 0x0000 and 0xFFFF */
517 } TMR_OCConfig_T;
518 
519 /**
520  * @brief    TMR BDT structure definition
521  */
522 typedef struct
523 {
524     TMR_RMOS_STATE_T       RMOS;
525     TMR_IMOS_STATE_T       IMOS;
526     TMR_LOCK_LEVEL_T       lockLevel;
527     uint16_t               deadTime;
528     TMR_BRK_STATE_T        BRKState;
529     TMR_BRK_POLARITY_T     BRKPolarity;
530     TMR_AUTOMATIC_OUTPUT_T automaticOutput;
531 } TMR_BDTConfig_T;
532 
533 /**
534  * @brief    TMR Input Capture Config struct definition
535  */
536 typedef struct
537 {
538     TMR_CHANNEL_T          channel;
539     TMR_IC_POLARITY_T      polarity;
540     TMR_IC_SELECTION_T     selection;
541     TMR_IC_PSC_T           prescaler;
542     uint16_t               filter;    /*!< This must between 0x00 and 0x0F */
543 } TMR_ICConfig_T;
544 
545 /**@} end of group TMR_Structures */
546 
547 /** @defgroup  TMR_Functions Functions
548   @{
549 */
550 
551 /* Reset and Configuration */
552 void TMR_Reset(TMR_T* tmr);
553 void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig);
554 void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OC1Config);
555 void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OC2Config);
556 void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OC3Config);
557 void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OC4Config);
558 void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig);
559 void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig);
560 void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig);
561 void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig);
562 void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig);
563 void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig);
564 void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode);
565 void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision);
566 void TMR_Enable(TMR_T* tmr);
567 void TMR_Disable(TMR_T* tmr);
568 
569 /* PWM Configuration */
570 void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig);
571 void TMR_EnablePWMOutputs(TMR_T* tmr);
572 void TMR_DisablePWMOutputs(TMR_T* tmr);
573 
574 /* DMA */
575 void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
576 void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource);
577 void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource);
578 
579 /* Configuration */
580 void TMR_ConfigInternalClock(TMR_T* tmr);
581 void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource);
582 void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
583                                 TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
584 void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
585                              TMR_EXTTRG_POL_T polarity, uint16_t filter);
586 void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
587                              TMR_EXTTRG_POL_T polarity, uint16_t filter);
588 void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
589                    TMR_EXTTRG_POL_T polarity, uint16_t filter);
590 void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode);
591 void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode);
592 void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
593 void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
594                                TMR_IC_POLARITY_T IC2Polarity);
595 void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
596 void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
597 void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
598 void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
599 void TMR_EnableAutoReload(TMR_T* tmr);
600 void TMR_DisableAutoReload(TMR_T* tmr);
601 void TMR_EnableSelectCOM(TMR_T* tmr);
602 void TMR_DisableSelectCOM(TMR_T* tmr);
603 void TMR_EnableCCDMA(TMR_T* tmr);
604 void TMR_DisableCCDMA(TMR_T* tmr);
605 void TMR_EnableCCPreload(TMR_T* tmr);
606 void TMR_DisableCCPreload(TMR_T* tmr);
607 void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
608 void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
609 void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
610 void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
611 void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
612 void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
613 void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
614 void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
615 void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
616 void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
617 void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
618 void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
619 void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
620 void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
621 void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
622 void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
623 void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
624 void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
625 void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
626 void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
627 void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
628 void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
629 void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
630 void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
631 void TMR_EnableUpdate(TMR_T* tmr);
632 void TMR_DisableUpdate(TMR_T* tmr);
633 void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource);
634 void TMR_EnableHallSensor(TMR_T* tmr);
635 void TMR_DisableHallSensor(TMR_T* tmr);
636 
637 void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource);
638 void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode);
639 void TMR_EnableMasterSlaveMode(TMR_T* tmr);
640 void TMR_DisableMasterSlaveMode(TMR_T* tmr);
641 void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter);
642 void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload);
643 void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1);
644 void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2);
645 void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3);
646 void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4);
647 void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
648 void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
649 void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
650 void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
651 
652 uint16_t TMR_ReadCaputer1(TMR_T* tmr);
653 uint16_t TMR_ReadCaputer2(TMR_T* tmr);
654 uint16_t TMR_ReadCaputer3(TMR_T* tmr);
655 uint16_t TMR_ReadCaputer4(TMR_T* tmr);
656 uint16_t TMR_ReadCounter(TMR_T* tmr);
657 uint16_t TMR_ReadPrescaler(TMR_T* tmr);
658 
659 /* Interrupts and Event */
660 void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt);
661 void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt);
662 void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources);
663 
664 /* flags */
665 uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag);
666 void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag);
667 uint16_t TMR_ReadIntFlag(TMR_T* tmr,  TMR_INT_T flag);
668 void TMR_ClearIntFlag(TMR_T* tmr,  uint16_t flag);
669 
670 /**@} end of group TMR_Functions*/
671 /**@} end of group TMR_Driver */
672 /**@} end of group APM32E10x_StdPeriphDriver*/
673 
674 #ifdef __cplusplus
675 }
676 #endif
677 
678 #endif /* __APM32E10X_TMR_H */
679