1 /*! 2 * @file apm32f0xx_rcm.h 3 * 4 * @brief This file contains all the functions prototypes for the RCM firmware library 5 * 6 * @version V1.0.2 7 * 8 * @date 2022-02-21 9 * 10 * @attention 11 * 12 * Copyright (C) 2020-2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 #ifndef __APM32F0XX_RCM_H 27 #define __APM32F0XX_RCM_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include "apm32f0xx.h" 34 35 /** @addtogroup APM32F0xx_StdPeriphDriver 36 @{ 37 */ 38 39 /** @addtogroup RCM_Driver RCM Driver 40 @{ 41 */ 42 43 /** @defgroup RCM_Macros Macros 44 @{ 45 */ 46 47 /**@} end of group RCM_Macros*/ 48 49 /** @defgroup RCM_Enumerations Enumerations 50 @{ 51 */ 52 53 /** 54 * @brief HSE enum 55 */ 56 typedef enum 57 { 58 RCM_HSE_CLOSE = 0x00, /*!< turn OFF the HSE oscillator */ 59 RCM_HSE_OPEN = 0x01, /*!< turn ON the HSE oscillator */ 60 RCM_HSE_BYPASS = 0x05, /*!< HSE oscillator bypassed with external clock */ 61 } RCM_HSE_T; 62 63 /** 64 * @brief LSE enum 65 */ 66 typedef enum 67 { 68 RCM_LSE_CLOSE = 0x00, /*!< turn OFF the LSE oscillator */ 69 RCM_LSE_OPEN = 0x01, /*!< turn ON the LSE oscillator */ 70 RCM_LSE_BYPASS = 0x05, /*!< LSE oscillator bypassed with external clock */ 71 } RCM_LSE_T; 72 73 /** 74 * @brief LSE_Drive enum 75 */ 76 typedef enum 77 { 78 RCM_LSE_DRIVE_Low = 0x00, /*!< LSE oscillator low drive capability */ 79 RCM_LSE_DRIVE_MediumLow, /*!< LSE oscillator medium low drive capability */ 80 RCM_LSE_DRIVE_MediumHigh, /*!< LSE oscillator medium high drive capability */ 81 RCM_LSE_DRIVE_High, /*!< LSE oscillator high drive capability */ 82 } RCM_LSE_DRIVE_T; 83 84 /** 85 * @brief System clock select 86 */ 87 typedef enum 88 { 89 RCM_PLL_SEL_HSI_DIV2, /*!< HSI clock divided by 2 selected as PLL clock source */ 90 RCM_PLL_SEL_HSI, /*!< HSI clock selected as PLL clock entry, only for APM32F072 and APM32F091 devices */ 91 RCM_PLL_SEL_HSE, /*!< HSE/CLKDIV1 selected as PLL clock entry */ 92 RCM_PLL_SEL_HSI48 /*!< HSI48 oscillator clock selected as PLL clock source, only for APM32F072 and APM32F091 devices */ 93 } RCM_PLL_SEL_T; 94 95 /** 96 * @brief PLL multiplication factor 97 */ 98 typedef enum 99 { 100 RCM_PLLMF_2, /*!< specifies the PLLMULCFG clock multiple factor as 2 */ 101 RCM_PLLMF_3, /*!< specifies the PLLMULCFG clock multiple factor as 3 */ 102 RCM_PLLMF_4, /*!< specifies the PLLMULCFG clock multiple factor as 4 */ 103 RCM_PLLMF_5, /*!< specifies the PLLMULCFG clock multiple factor as 5 */ 104 RCM_PLLMF_6, /*!< specifies the PLLMULCFG clock multiple factor as 6 */ 105 RCM_PLLMF_7, /*!< specifies the PLLMULCFG clock multiple factor as 7 */ 106 RCM_PLLMF_8, /*!< specifies the PLLMULCFG clock multiple factor as 8 */ 107 RCM_PLLMF_9, /*!< specifies the PLLMULCFG clock multiple factor as 9 */ 108 RCM_PLLMF_10, /*!< specifies the PLLMULCFG clock multiple factor as 10 */ 109 RCM_PLLMF_11, /*!< specifies the PLLMULCFG clock multiple factor as 11 */ 110 RCM_PLLMF_12, /*!< specifies the PLLMULCFG clock multiple factor as 12 */ 111 RCM_PLLMF_13, /*!< specifies the PLLMULCFG clock multiple factor as 13 */ 112 RCM_PLLMF_14, /*!< specifies the PLLMULCFG clock multiple factor as 14 */ 113 RCM_PLLMF_15, /*!< specifies the PLLMULCFG clock multiple factor as 15 */ 114 RCM_PLLMF_16, /*!< specifies the PLLMULCFG clock multiple factor as 16 */ 115 } RCM_PLLMF_T; 116 117 /** 118 * @brief RCM clock division 119 */ 120 typedef enum 121 { 122 RCM_CLK_DIV_1, /*!< specifies the PLLDIVCFG clock division factor as 1 */ 123 RCM_CLK_DIV_2, /*!< specifies the PLLDIVCFG clock division factor as 2 */ 124 RCM_CLK_DIV_3, /*!< specifies the PLLDIVCFG clock division factor as 3 */ 125 RCM_CLK_DIV_4, /*!< specifies the PLLDIVCFG clock division factor as 4 */ 126 RCM_CLK_DIV_5, /*!< specifies the PLLDIVCFG clock division factor as 5 */ 127 RCM_CLK_DIV_6, /*!< specifies the PLLDIVCFG clock division factor as 6 */ 128 RCM_CLK_DIV_7, /*!< specifies the PLLDIVCFG clock division factor as 7 */ 129 RCM_CLK_DIV_8, /*!< specifies the PLLDIVCFG clock division factor as 8 */ 130 RCM_CLK_DIV_9, /*!< specifies the PLLDIVCFG clock division factor as 9 */ 131 RCM_CLK_DIV_10, /*!< specifies the PLLDIVCFG clock division factor as 10 */ 132 RCM_CLK_DIV_11, /*!< specifies the PLLDIVCFG clock division factor as 11 */ 133 RCM_CLK_DIV_12, /*!< specifies the PLLDIVCFG clock division factor as 12 */ 134 RCM_CLK_DIV_13, /*!< specifies the PLLDIVCFG clock division factor as 13 */ 135 RCM_CLK_DIV_14, /*!< specifies the PLLDIVCFG clock division factor as 14 */ 136 RCM_CLK_DIV_15, /*!< specifies the PLLDIVCFG clock division factor as 15 */ 137 RCM_CLK_DIV_16, /*!< specifies the PLLDIVCFG clock division factor as 16 */ 138 } RCM_CLK_DIV_T; 139 140 /** 141 * @brief Clock output control 142 */ 143 typedef enum 144 { 145 RCM_COC_NO_CLOCK, /*!< No clock selected */ 146 RCM_COC_HSI14, /*!< HSI14 oscillator clock selected */ 147 RCM_COC_LSI, /*!< LSI oscillator clock selected */ 148 RCM_COC_LSE, /*!< LSE oscillator clock selected */ 149 RCM_COC_SYSCLK, /*!< System clock selected */ 150 RCM_COC_HSI, /*!< HSI oscillator clock selected */ 151 RCM_COC_HSE, /*!< HSE oscillator clock selected */ 152 RCM_COC_PLLCLK_DIV_2, /*!< PLL clock divided by 2 selected */ 153 RCM_COC_HSI48, /*!< HSI48 oscillator clock selected, only for APM32F072 and APM32F091 devices */ 154 RCM_COC_PLLCLK /*!< PLL clock selected */ 155 } RCM_COCCLK_T; 156 157 /** 158 * @brief Clock output division 159 */ 160 typedef enum 161 { 162 RCM_COC_DIV_1, /*!< MCOSEL clock is divided by 1 */ 163 RCM_COC_DIV_2, /*!< MCOSEL clock is divided by 2 */ 164 RCM_COC_DIV_4, /*!< MCOSEL clock is divided by 4 */ 165 RCM_COC_DIV_8, /*!< MCOSEL clock is divided by 8 */ 166 RCM_COC_DIV_16, /*!< MCOSEL clock is divided by 16 */ 167 RCM_COC_DIV_32, /*!< MCOSEL clock is divided by 32 */ 168 RCM_COC_DIV_64, /*!< MCOSEL clock is divided by 64 */ 169 RCM_COC_DIV_128, /*!< MCOSEL clock is divided by 128 */ 170 } RCM_COCPRE_T; 171 172 /** 173 * @brief System clock select 174 */ 175 typedef enum 176 { 177 RCM_SYSCLK_SEL_HSI, /*!< HSI selected as system clock source */ 178 RCM_SYSCLK_SEL_HSE, /*!< HSE selected as system clock source */ 179 RCM_SYSCLK_SEL_PLL, /*!< PLL selected as system clock source */ 180 RCM_SYSCLK_SEL_HSI48, /*!< HSI48 selected as system clock source, only for APM32F072 and APM32F091 devices */ 181 } RCM_SYSCLK_SEL_T; 182 183 /** 184 * @brief AHB divider Number 185 */ 186 typedef enum 187 { 188 RCM_SYSCLK_DIV_1 = 7, /*!< AHB clock = SYSCLK */ 189 RCM_SYSCLK_DIV_2, /*!< AHB clock = SYSCLK/2 */ 190 RCM_SYSCLK_DIV_4, /*!< AHB clock = SYSCLK/4 */ 191 RCM_SYSCLK_DIV_8, /*!< AHB clock = SYSCLK/8 */ 192 RCM_SYSCLK_DIV_16, /*!< AHB clock = SYSCLK/16 */ 193 RCM_SYSCLK_DIV_64, /*!< AHB clock = SYSCLK/64 */ 194 RCM_SYSCLK_DIV_128, /*!< AHB clock = SYSCLK/128 */ 195 RCM_SYSCLK_DIV_256, /*!< AHB clock = SYSCLK/256 */ 196 RCM_SYSCLK_DIV_512, /*!< AHB clock = SYSCLK/512 */ 197 } RCM_AHBDIV_T; 198 199 /** 200 * @brief APB divider Number 201 */ 202 typedef enum 203 { 204 RCM_HCLK_DIV_1 = 3, /*!< APB clock = HCLK */ 205 RCM_HCLK_DIV_2, /*!< APB clock = HCLK/2 */ 206 RCM_HCLK_DIV_4, /*!< APB clock = HCLK/4 */ 207 RCM_HCLK_DIV_8, /*!< APB clock = HCLK/8 */ 208 RCM_HCLK_DIV_16 /*!< APB clock = HCLK/16 */ 209 } RCM_APBDIV_T; 210 211 /** 212 * @brief CEC divider Number 213 */ 214 typedef enum 215 { 216 RCM_CECCLK_HSI_DIV_224, /*!< CEC clock = HSI/244 (32768Hz) */ 217 RCM_CECCLK_LSI_DIV, /*!< CEC clock = LSI */ 218 } RCM_CECCLK_T; 219 220 /** 221 * @brief I2C clock source selectio 222 */ 223 typedef enum 224 { 225 RCM_I2C1CLK_HSI, /*!< I2C1 clock = HSI */ 226 RCM_I2C1CLK_SYSCLK, /*!< I2C1 clock = System Clock */ 227 } RCM_I2CCLK_T; 228 229 /** 230 * @brief USART clock source selectio 231 */ 232 typedef enum 233 { 234 RCM_USART1CLK_PCLK = ((uint32_t)0x00010000), /*!< USART1 clock = APB Clock (PCLK) */ 235 RCM_USART1CLK_SYSCLK = ((uint32_t)0x00010001), /*!< USART1 clock = System Clock */ 236 RCM_USART1CLK_LSE = ((uint32_t)0x00010002), /*!< USART1 clock = LSE Clock */ 237 RCM_USART1CLK_HSI = ((uint32_t)0x00010003), /*!< USART1 clock = HSI Clock */ 238 RCM_USART2CLK_PCLK = ((uint32_t)0x00020000), /*!< USART2 clock = APB Clock (PCLK), only for APM32F072 and APM32F091 devices */ 239 RCM_USART2CLK_SYSCLK = ((uint32_t)0x00020001), /*!< USART2 clock = System Clock, only for APM32F072 and APM32F091 devices */ 240 RCM_USART2CLK_LSE = ((uint32_t)0x00020002), /*!< USART2 clock = LSE Clock, only for APM32F072 and APM32F091 devices */ 241 RCM_USART2CLK_HSI = ((uint32_t)0x00020003), /*!< USART2 clock = HSI Clock, only for APM32F072 and APM32F091 devices */ 242 RCM_USART3CLK_PCLK = ((uint32_t)0x00040000), /*!< USART3 clock = APB Clock (PCLK), only for APM32F091 devices */ 243 RCM_USART3CLK_SYSCLK = ((uint32_t)0x00040001), /*!< USART3 clock = System Clock, only for APM32F091 devices */ 244 RCM_USART3CLK_LSE = ((uint32_t)0x00040002), /*!< USART3 clock = LSE Clock, only for APM32F091 devices */ 245 RCM_USART3CLK_HSI = ((uint32_t)0x00040003), /*!< USART3 clock = HSI Clock, only for APM32F091 devices */ 246 } RCM_USARTCLK_T; 247 248 /** 249 * @brief USB clock source selection 250 */ 251 typedef enum 252 { 253 RCM_USBCLK_HSI48, /*!<hsi48 selected as USB clock, only for APM32F072 devices */ 254 RCM_USBCLK_PLLCLK, /*!<PLL clock selected as USB clock, only for APM32F072 devices */ 255 } RCM_USBCLK_T; 256 257 /** 258 * @brief RTC clock select 259 */ 260 typedef enum 261 { 262 RCM_RTCCLK_LSE = 0X01, /*!< LSE selected as RTC clock */ 263 RCM_RTCCLK_LSI, /*!< LSI selected as RTC clock */ 264 RCM_RTCCLK_HSE_DIV_32 /*!< HSE divided by 32 selected as RTC clock */ 265 } RCM_RTCCLK_T; 266 267 /** 268 * @brief AHB peripheral 269 */ 270 typedef enum 271 { 272 RCM_AHB_PERIPH_DMA1 = BIT0, /*!< DMA1 peripheral clock */ 273 RCM_AHB_PERIPH_DMA2 = BIT1, /*!< DMA2 peripheral clock */ 274 RCM_AHB_PERIPH_SRAM = BIT2, /*!< SRAM peripheral clock */ 275 RCM_AHB_PERIPH_FPU = BIT4, /*!< FMC peripheral clock */ 276 RCM_AHB_PERIPH_CRC = BIT6, /*!< CRC peripheral clock */ 277 RCM_AHB_PERIPH_GPIOA = BIT17, /*!< GPIOA peripheral clock */ 278 RCM_AHB_PERIPH_GPIOB = BIT18, /*!< GPIOB peripheral clock */ 279 RCM_AHB_PERIPH_GPIOC = BIT19, /*!< GPIOC peripheral clock */ 280 RCM_AHB_PERIPH_GPIOD = BIT20, /*!< GPIOD peripheral clock */ 281 RCM_AHB_PERIPH_GPIOE = BIT21, /*!< GPIOE peripheral clock, only for APM32F072 and APM32F091 devices */ 282 RCM_AHB_PERIPH_GPIOF = BIT22, /*!< GPIOF peripheral clock */ 283 RCM_AHB_PERIPH_TSC = BIT24, /*!< TSC peripheral clock */ 284 } RCM_AHB_PERIPH_T; 285 286 /** 287 * @brief AHB2 peripheral 288 */ 289 typedef enum 290 { 291 RCM_APB2_PERIPH_SYSCFG = BIT0, /*!< SYSCFG peripheral clock */ 292 RCM_APB2_PERIPH_USART6 = BIT5, /*!< USART6 peripheral clock */ 293 RCM_APB2_PERIPH_USART7 = BIT6, /*!< USART7 peripheral clock */ 294 RCM_APB2_PERIPH_USART8 = BIT7, /*!< USART8 peripheral clock */ 295 RCM_APB2_PERIPH_ADC1 = BIT9, /*!< ADC1 peripheral clock */ 296 RCM_APB2_PERIPH_TMR1 = BIT11, /*!< TMR1 peripheral clock */ 297 RCM_APB2_PERIPH_SPI1 = BIT12, /*!< SPI1 peripheral clock */ 298 RCM_APB2_PERIPH_USART1 = BIT14, /*!< USART1 peripheral clock */ 299 RCM_APB2_PERIPH_TMR15 = BIT16, /*!< TMR15 peripheral clock */ 300 RCM_APB2_PERIPH_TMR16 = BIT17, /*!< TMR16 peripheral clock */ 301 RCM_APB2_PERIPH_TMR17 = BIT18, /*!< TMR17 peripheral clock */ 302 RCM_APB2_PERIPH_DBGMCU = BIT22, /*!< DBGMCU peripheral clock */ 303 } RCM_APB2_PERIPH_T; 304 305 /** 306 * @brief AHB1 peripheral 307 */ 308 typedef enum 309 { 310 RCM_APB1_PERIPH_TMR2 = BIT0, /*!< TMR2 peripheral clock, only for APM32F072 and APM32F091 devices */ 311 RCM_APB1_PERIPH_TMR3 = BIT1, /*!< TMR3 peripheral clock */ 312 RCM_APB1_PERIPH_TMR6 = BIT4, /*!< TMR6 peripheral clock */ 313 RCM_APB1_PERIPH_TMR7 = BIT5, /*!< TMR7 peripheral clock, only for APM32F072 and APM32F091 devices */ 314 RCM_APB1_PERIPH_TMR14 = BIT8, /*!< TMR14 peripheral clock */ 315 RCM_APB1_PERIPH_WWDT = BIT11, /*!< WWDT peripheral clock */ 316 RCM_APB1_PERIPH_SPI2 = BIT14, /*!< SPI2 peripheral clock */ 317 RCM_APB1_PERIPH_USART2 = BIT17, /*!< USART2 peripheral clock */ 318 RCM_APB1_PERIPH_USART3 = BIT18, /*!< USART3 peripheral clock, only for APM32F072 and APM32F091 devices */ 319 RCM_APB1_PERIPH_USART4 = BIT19, /*!< USART4 peripheral clock, only for APM32F072 and APM32F091 devices */ 320 RCM_APB1_PERIPH_USART5 = BIT20, /*!< USART5 peripheral clock, only for APM32F091 devices */ 321 RCM_APB1_PERIPH_I2C1 = BIT21, /*!< I2C1 peripheral clock */ 322 RCM_APB1_PERIPH_I2C2 = BIT22, /*!< I2C2 peripheral clock */ 323 RCM_APB1_PERIPH_USB = BIT23, /*!< USB peripheral clock only for APM32F072 devices */ 324 RCM_APB1_PERIPH_CAN = BIT25, /*!< CAN peripheral clock, only for APM32F072 and APM32F091 devices */ 325 RCM_APB1_PERIPH_CRS = BIT27, /*!< CRS peripheral clock, only for APM32F072 and APM32F091 devices */ 326 RCM_APB1_PERIPH_PMU = BIT28, /*!< PMU peripheral clock */ 327 RCM_APB1_PERIPH_DAC = BIT29, /*!< DAC peripheral clock, only for APM32F072 and APM32F091 devices */ 328 RCM_APB1_PERIPH_CEC = BIT30, /*!< CEC peripheral clock, only for APM32F072 and APM32F091 devices */ 329 } RCM_APB1_PERIPH_T; 330 331 /** 332 * @brief RCM Interrupt Source 333 */ 334 typedef enum 335 { 336 RCM_INT_LSIRDY = BIT0, /*!< LSI ready interrupt */ 337 RCM_INT_LSERDY = BIT1, /*!< LSE ready interrupt */ 338 RCM_INT_HSIRDY = BIT2, /*!< HSI ready interrupt */ 339 RCM_INT_HSERDY = BIT3, /*!< HSE ready interrupt */ 340 RCM_INT_PLLRDY = BIT4, /*!< PLL ready interrupt */ 341 RCM_INT_HSI14RDY = BIT5, /*!< HSI14 ready interrupt */ 342 RCM_INT_HSI48RDY = BIT6, /*!< HSI48 ready interrupt (Only for APM32F072 and APM32F091 devices) */ 343 RCM_INT_CSS = BIT7 /*!< Clock security system interrupt */ 344 } RCM_INT_T; 345 346 /** 347 * @brief RCM FLAG define 348 */ 349 typedef enum 350 { 351 RCM_FLAG_HSIRDY = 0x001, /*!< HSI Ready Flag */ 352 RCM_FLAG_HSERDY = 0x011, /*!< HSE Ready Flag */ 353 RCM_FLAG_PLLRDY = 0x019, /*!< PLL Ready Flag */ 354 RCM_FLAG_LSERDY = 0x101, /*!< LSE Ready Flag */ 355 RCM_FLAG_LSIRDY = 0x201, /*!< LSI Ready Flag */ 356 RCM_FLAG_V18PRRST = 0x217, /*!< Software reset flag */ 357 RCM_FLAG_OBRST = 0x219, /*!< Option byte loader reset flag */ 358 RCM_FLAG_PINRST = 0x21A, /*!< PIN reset flag */ 359 RCM_FLAG_PWRRST = 0x21B, /*!< POR/PDR reset flag */ 360 RCM_FLAG_SWRST = 0x21C, /*!< Software reset flag */ 361 RCM_FLAG_IWDTRST = 0x21D, /*!< Independent watchdog reset flag */ 362 RCM_FLAG_WWDTRST = 0x21E, /*!< Window watchdog reset flag */ 363 RCM_FLAG_LPRRST = 0x21F, /*!< Low-power reset flag */ 364 RCM_FLAG_HSI14RDY = 0x301, /*!< HSI14 Ready Flag */ 365 RCM_FLAG_HSI48RDY = 0x311, /*!< HSI48 Ready Flag (Only for APM32F072 devices and APM32F091 devices) */ 366 } RCM_FLAG_T; 367 368 /**@} end of group RCM_Enumerations*/ 369 370 /** @defgroup RCM_Structures Structures 371 @{ 372 */ 373 374 /**@} end of group RCM_Structures*/ 375 376 /** @defgroup RCM_Variables Variables 377 @{ 378 */ 379 380 /**@} end of group RCM_Variables*/ 381 382 /** @defgroup RCM_Fuctions Fuctions 383 @{ 384 */ 385 386 /** Function description */ 387 388 void RCM_Reset(void); 389 390 void RCM_ConfigHSE(RCM_HSE_T state); 391 uint8_t RCM_WaitHSEReady(void); 392 void RCM_SetHSITrim(uint8_t HSITrim); 393 void RCM_EnableHSI(void); 394 void RCM_DisableHSI(void); 395 396 void RCM_SetHSI14Trim(uint8_t HSI14Trim); 397 void RCM_EnableHSI14(void); 398 void RCM_DisableHSI14(void); 399 void RCM_EnableHSI14ADC(void); 400 void RCM_DisableHSI14ADC(void); 401 402 void RCM_ConfigLSE(RCM_LSE_T state); 403 void RCM_ConfigDriveLSE(RCM_LSE_DRIVE_T state); 404 405 void RCM_EnableLSI(void); 406 void RCM_DisableLSI(void); 407 408 void RCM_ConfigPLL(RCM_PLL_SEL_T pllSelect, RCM_PLLMF_T pllMf); 409 void RCM_EnablePLL(void); 410 void RCM_DisablePLL(void); 411 412 void RCM_EnableHSI48(void); /*!< Only for APM32F072 and APM32F091 devices */ 413 void RCM_DisableHSI48(void); /*!< Only for APM32F072 and APM32F091 devices */ 414 uint32_t RCM_ReadHSI48CalibrationValue(void); /*!< Only for APM32F072 and APM32F091 devices */ 415 416 void RCM_ConfigCLKDIV(RCM_CLK_DIV_T state); 417 418 void RCM_EnableCCS(void); 419 void RCM_DisableCCS(void); 420 421 #if defined (APM32F030) || defined (APM32F051) 422 void RCM_ConfigCOC(RCM_COCCLK_T cocClock); 423 #else 424 void RCM_ConfigCOC(RCM_COCCLK_T cocClock, RCM_COCPRE_T divided); 425 #endif 426 427 void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect); 428 RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void); 429 430 void RCM_ConfigAHB(RCM_AHBDIV_T AHBDiv); 431 void RCM_ConfigAPB(RCM_APBDIV_T APBDiv); 432 void RCM_ConfigCECCLK(RCM_CECCLK_T CECClk); 433 void RCM_ConfigI2CCLK(RCM_I2CCLK_T I2CCLk); 434 void RCM_ConfigUSARTCLK(RCM_USARTCLK_T USARTClk); 435 void RCM_ConfigUSBCLK(RCM_USBCLK_T USBClk); /*!< Only for APM32F072 devices */ 436 437 uint32_t RCM_ReadSYSCLKFreq(void); 438 uint32_t RCM_ReadHCLKFreq(void); 439 uint32_t RCM_ReadPCLKFreq(void); 440 uint32_t RCM_ReadADCCLKFreq(void); 441 uint32_t RCM_ReadCECCLKFreq(void); 442 uint32_t RCM_ReadI2C1CLKFreq(void); 443 uint32_t RCM_ReadUSART1CLKFreq(void); 444 uint32_t RCM_ReadUSART2CLKFreq(void); 445 uint32_t RCM_ReadUSBCLKFreq(void); 446 447 void RCM_ConfigRTCCLK(RCM_RTCCLK_T RTCClk); 448 void RCM_EnableRTCCLK(void); 449 void RCM_DisableRTCCLK(void); 450 451 void RCM_EnableBackupReset(void); 452 void RCM_DisableBackupReset(void); 453 454 void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph); 455 void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph); 456 void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph); 457 void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph); 458 void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph); 459 void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph); 460 461 void RCM_EnableAHBPeriphReset(uint32_t AHBPeriph); 462 void RCM_DisableAHBPeriphReset(uint32_t AHBPeriph); 463 void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph); 464 void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph); 465 void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph); 466 void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph); 467 468 void RCM_EnableInterrupt(uint8_t interrupt); 469 void RCM_DisableInterrupt(uint8_t interrupt); 470 uint16_t RCM_ReadStatusFlag(RCM_FLAG_T flag); 471 void RCM_ClearStatusFlag(void); 472 uint8_t RCM_ReadIntFlag(RCM_INT_T flag); 473 void RCM_ClearIntFlag(uint8_t flag); 474 475 #ifdef __cplusplus 476 } 477 #endif 478 479 #endif /* __APM32F0XX_RCM_H */ 480 481 /**@} end of group RCM_Functions*/ 482 /**@} end of group RCM_Driver*/ 483 /**@} end of group APM32F0xx_StdPeriphDriver*/ 484