1 /*!
2 * @file apm32f10x_dma.c
3 *
4 * @brief This file provides all the DMA firmware functions
5 *
6 * @version V1.0.4
7 *
8 * @date 2022-12-01
9 *
10 * @attention
11 *
12 * Copyright (C) 2020-2022 Geehy Semiconductor
13 *
14 * You may not use this file except in compliance with the
15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16 *
17 * The program is only for reference, which is distributed in the hope
18 * that it will be useful and instructional for customers to develop
19 * their software. Unless required by applicable law or agreed to in
20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23 * and limitations under the License.
24 */
25
26 #include "apm32f10x_dma.h"
27
28 /** @addtogroup APM32F10x_StdPeriphDriver
29 @{
30 */
31
32 /** @addtogroup DMA_Driver DMA Driver
33 * @brief DMA driver modules
34 @{
35 */
36
37 /** @defgroup DMA_Functions Functions
38 @{
39 */
40
41 /*!
42 * @brief Reset specified DMA Channel registers to their default reset
43 *
44 * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5).
45 *
46 * @retval None
47 *
48 * @note DMA2 Channel only for APM32 High density devices.
49 */
DMA_Reset(DMA_Channel_T * channel)50 void DMA_Reset(DMA_Channel_T* channel)
51 {
52 channel->CHCFG_B.CHEN = BIT_RESET;
53 channel->CHCFG = 0;
54 channel->CHNDATA = 0;
55 channel->CHMADDR = 0;
56 channel->CHPADDR = 0;
57
58 if (channel == DMA1_Channel1)
59 {
60 DMA1->INTFCLR |= 0xFFFFFFF0;
61 }
62 else if (channel == DMA1_Channel2)
63 {
64 DMA1->INTFCLR |= 0xFFFFFF0F;
65 }
66 else if (channel == DMA1_Channel3)
67 {
68 DMA1->INTFCLR |= 0xFFFFF0FF;
69 }
70 else if (channel == DMA1_Channel4)
71 {
72 DMA1->INTFCLR |= 0xFFFF0FFF;
73 }
74 else if (channel == DMA1_Channel5)
75 {
76 DMA1->INTFCLR |= 0xFFF0FFFF;
77 }
78 else if (channel == DMA1_Channel6)
79 {
80 DMA1->INTFCLR |= 0xFF0FFFFF;
81 }
82 else if (channel == DMA1_Channel7)
83 {
84 DMA1->INTFCLR |= 0xF0FFFFFF;
85 }
86 else if (channel == DMA2_Channel1)
87 {
88 DMA2->INTFCLR |= 0xFFFFFFF0;
89 }
90 else if (channel == DMA2_Channel2)
91 {
92 DMA2->INTFCLR |= 0xFFFFFF0F;
93 }
94 else if (channel == DMA2_Channel3)
95 {
96 DMA2->INTFCLR |= 0xFFFFF0FF;
97 }
98 else if (channel == DMA2_Channel4)
99 {
100 DMA2->INTFCLR |= 0xFFFF0FFF;
101 }
102 else if (channel == DMA2_Channel5)
103 {
104 DMA2->INTFCLR |= 0xFFF0FFFF;
105 }
106 }
107
108 /*!
109 * @brief Configs specified DMA Channel through a structure.
110 *
111 * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
112 *
113 * @param dmaConfig: Point to a DMA_Config_T structure
114 *
115 * @retval None
116 *
117 * @note DMA2 Channel only for APM32 High density devices.
118 */
DMA_Config(DMA_Channel_T * channel,DMA_Config_T * dmaConfig)119 void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig)
120 {
121 channel->CHCFG_B.DIRCFG = dmaConfig->dir;
122 channel->CHCFG_B.CIRMODE = dmaConfig->loopMode;
123 channel->CHCFG_B.PERIMODE = dmaConfig->peripheralInc;
124 channel->CHCFG_B.MIMODE = dmaConfig->memoryInc;
125 channel->CHCFG_B.PERSIZE = dmaConfig->peripheralDataSize;
126 channel->CHCFG_B.MEMSIZE = dmaConfig->memoryDataSize;
127 channel->CHCFG_B.CHPL = dmaConfig->priority;
128 channel->CHCFG_B.M2MMODE = dmaConfig->M2M;
129
130 channel->CHNDATA = dmaConfig->bufferSize;
131 channel->CHPADDR = dmaConfig->peripheralBaseAddr;
132 channel->CHMADDR = dmaConfig->memoryBaseAddr;
133 }
134
135 /*!
136 * @brief Populate the structure with default values.
137 *
138 * @param dmaConfig: Point to a DMA_Config_T structure.
139 *
140 * @retval None
141 */
DMA_ConfigStructInit(DMA_Config_T * dmaConfig)142 void DMA_ConfigStructInit(DMA_Config_T* dmaConfig)
143 {
144 dmaConfig->peripheralBaseAddr = 0;
145 dmaConfig->memoryBaseAddr = 0;
146 dmaConfig->dir = DMA_DIR_PERIPHERAL_SRC;
147 dmaConfig->bufferSize = 0;
148 dmaConfig->peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
149 dmaConfig->memoryInc = DMA_MEMORY_INC_DISABLE;
150 dmaConfig->peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_BYTE;
151 dmaConfig->memoryDataSize = DMA_MEMORY_DATA_SIZE_BYTE;
152 dmaConfig->loopMode = DMA_MODE_NORMAL;
153 dmaConfig->priority = DMA_PRIORITY_LOW;
154 dmaConfig->M2M = DMA_M2MEN_DISABLE;
155 }
156
157 /*!
158 * @brief Enable the specified DMA Channel
159 *
160 * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
161 *
162 * @retval None
163 *
164 * @note DMA2 Channel only for APM32 High density devices.
165 */
DMA_Enable(DMA_Channel_T * channel)166 void DMA_Enable(DMA_Channel_T* channel)
167 {
168 channel->CHCFG_B.CHEN = ENABLE;
169 }
170
171 /*!
172 * @brief Disable the specified DMA Channel
173 *
174 * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
175 *
176 * @retval None
177 *
178 * @note DMA2 Channel only for APM32 High density devices.
179 */
DMA_Disable(DMA_Channel_T * channel)180 void DMA_Disable(DMA_Channel_T* channel)
181 {
182 channel->CHCFG_B.CHEN = DISABLE;
183 }
184
185 /*!
186 * @brief Configs the number of data units in the channel.
187 *
188 * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
189 *
190 * @param dataNumber:The number of data units in the current DMA Channel transfer.
191 *
192 * @retval None
193 *
194 * @note DMA2 Channel only for APM32 High density devices.
195 */
DMA_ConfigDataNumber(DMA_Channel_T * channel,uint16_t dataNumber)196 void DMA_ConfigDataNumber(DMA_Channel_T* channel, uint16_t dataNumber)
197 {
198 channel->CHNDATA = dataNumber;
199 }
200
201 /*!
202 * @brief Read the number of data units in the channel
203 *
204 * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
205 *
206 * @retval The number of CHNDATA value
207 *
208 * @note DMA2 Channel only for APM32 High density devices.
209 */
DMA_ReadDataNumber(DMA_Channel_T * channel)210 uint16_t DMA_ReadDataNumber(DMA_Channel_T* channel)
211 {
212 return channel->CHNDATA;
213 }
214
215 /*!
216 * @brief Enables the specified DMA Channel interrupts.
217 *
218 * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
219 *
220 * @param interrupt: DMA interrupts sources to selsct
221 * This parameter can be any combination of the following values:
222 * @arg DMA_INT_TC : All Transfer Complete Interrupt
223 * @arg DMA_INT_HT : Half Transfer Complete Interrupt
224 * @arg DMA_INT_TERR : Transfer Error Occur Interrupt
225 *
226 * @retval None
227 *
228 * @note DMA2 Channel only for APM32 High density devices.
229 */
DMA_EnableInterrupt(DMA_Channel_T * channel,uint32_t interrupt)230 void DMA_EnableInterrupt(DMA_Channel_T* channel, uint32_t interrupt)
231 {
232 channel->CHCFG |= interrupt;
233 }
234
235 /*!
236 * @brief Disable the specified DMA Channel interrupts.
237 *
238 * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5)
239 *
240 * @param interrupt: DMA interrupts sources to selsct
241 * This parameter can be any combination of the following values:
242 * @arg DMA_INT_TC : All Transfer Complete Interrupt
243 * @arg DMA_INT_HT : Half Transfer Complete Interrupt
244 * @arg DMA_INT_TERR : Transfer Error Occur Interrupt
245 *
246 * @retval None
247 *
248 * @note DMA2 Channel only for APM32 High density devices.
249 */
DMA_DisableInterrupt(DMA_Channel_T * channel,uint32_t interrupt)250 void DMA_DisableInterrupt(DMA_Channel_T* channel, uint32_t interrupt)
251 {
252 channel->CHCFG &= ~interrupt;
253 }
254
255 /*!
256 * @brief Read whether the specifie DMA Channel flag is set or not.
257 *
258 * @param flag: the flag to check.
259 * This parameter can be one of the following values:
260 * @arg DMA1_FLAG_GINT1: DMA1 Channel 1 global flag.
261 * @arg DMA1_FLAG_TC1: DMA1 Channel 1 transfer complete flag.
262 * @arg DMA1_FLAG_HT1: DMA1 Channel 1 half transfer flag.
263 * @arg DMA1_FLAG_TERR1: DMA1 Channel 1 transfer error flag.
264 * @arg DMA1_FLAG_GINT2: DMA1 Channel2 global flag.
265 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
266 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
267 * @arg DMA1_FLAG_TERR2: DMA1 Channel2 transfer error flag.
268 * @arg DMA1_FLAG_GINT3: DMA1 Channel3 global flag.
269 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
270 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
271 * @arg DMA1_FLAG_TERR3: DMA1 Channel3 transfer error flag.
272 * @arg DMA1_FLAG_GINT4: DMA1 Channel4 global flag.
273 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
274 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
275 * @arg DMA1_FLAG_TERR4: DMA1 Channel4 transfer error flag.
276 * @arg DMA1_FLAG_GINT5: DMA1 Channel5 global flag.
277 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
278 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
279 * @arg DMA1_FLAG_TERR5: DMA1 Channel5 transfer error flag.
280 * @arg DMA1_FLAG_GINT6: DMA1 Channel6 global flag.
281 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
282 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
283 * @arg DMA1_FLAG_TERR6: DMA1 Channel6 transfer error flag.
284 * @arg DMA1_FLAG_GINT7: DMA1 Channel7 global flag.
285 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
286 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
287 * @arg DMA1_FLAG_TERR7: DMA1 Channel7 transfer error flag.
288 *
289 * @arg DMA2_FLAG_GINT1: DMA2 Channel 1 global flag.
290 * @arg DMA2_FLAG_TC1: DMA2 Channel 1 transfer complete flag.
291 * @arg DMA2_FLAG_HT1: DMA2 Channel 1 half transfer flag.
292 * @arg DMA2_FLAG_TERR1: DMA2 Channel 1 transfer error flag.
293 * @arg DMA2_FLAG_GINT2: DMA2 Channel 2 global flag.
294 * @arg DMA2_FLAG_TC2: DMA2 Channel 2 transfer complete flag.
295 * @arg DMA2_FLAG_HT2: DMA2 Channel 2 half transfer flag.
296 * @arg DMA2_FLAG_TERR2: DMA2 Channel 2 transfer error flag.
297 * @arg DMA2_FLAG_GINT3: DMA2 Channel 3 global flag.
298 * @arg DMA2_FLAG_TC3: DMA2 Channel 3 transfer complete flag.
299 * @arg DMA2_FLAG_HT3: DMA2 Channel 3 half transfer flag.
300 * @arg DMA2_FLAG_TERR3: DMA2 Channel 3 transfer error flag.
301 * @arg DMA2_FLAG_GINT4: DMA2 Channel 4 global flag.
302 * @arg DMA2_FLAG_TC4: DMA2 Channel 4 transfer complete flag.
303 * @arg DMA2_FLAG_HT4: DMA2 Channel 4 half transfer flag.
304 * @arg DMA2_FLAG_TERR4: DMA2 Channel 4 transfer error flag.
305 * @arg DMA2_FLAG_GINT5: DMA2 Channel 5 global flag.
306 * @arg DMA2_FLAG_TC5: DMA2 Channel 5 transfer complete flag.
307 * @arg DMA2_FLAG_HT5: DMA2 Channel 5 half transfer flag.
308 * @arg DMA2_FLAG_TERR5: DMA2 Channel 5 transfer error flag.
309 *
310 * @retval Flag State
311 *
312 * @note DMA2 Channel only for APM32 High density devices.
313 */
DMA_ReadStatusFlag(DMA_FLAG_T flag)314 uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag)
315 {
316 if ((flag & 0x10000000) != RESET)
317 {
318 if ((DMA2->INTSTS & flag) != RESET)
319 {
320 return SET ;
321 }
322 else
323 {
324 return RESET ;
325 }
326 }
327 else
328 {
329 if ((DMA1->INTSTS & flag) != RESET)
330 {
331 return SET ;
332 }
333 else
334 {
335 return RESET ;
336 }
337 }
338 }
339
340 /*!
341 * @brief Clears the specifie DMA Channel's flags.
342 *
343 * @param flag:the flag to Clear.
344 * This parameter can be any combination of the following values:
345 * @arg DMA1_FLAG_GINT1: DMA1 Channel 1 global flag.
346 * @arg DMA1_FLAG_TC1: DMA1 Channel 1 transfer complete flag.
347 * @arg DMA1_FLAG_HT1: DMA1 Channel 1 half transfer flag.
348 * @arg DMA1_FLAG_TERR1: DMA1 Channel 1 transfer error flag.
349 * @arg DMA1_FLAG_GINT2: DMA1 Channel2 global flag.
350 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
351 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
352 * @arg DMA1_FLAG_TERR2: DMA1 Channel2 transfer error flag.
353 * @arg DMA1_FLAG_GINT3: DMA1 Channel3 global flag.
354 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
355 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
356 * @arg DMA1_FLAG_TERR3: DMA1 Channel3 transfer error flag.
357 * @arg DMA1_FLAG_GINT4: DMA1 Channel4 global flag.
358 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
359 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
360 * @arg DMA1_FLAG_TERR4: DMA1 Channel4 transfer error flag.
361 * @arg DMA1_FLAG_GINT5: DMA1 Channel5 global flag.
362 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
363 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
364 * @arg DMA1_FLAG_TERR5: DMA1 Channel5 transfer error flag.
365 * @arg DMA1_FLAG_GINT6: DMA1 Channel6 global flag.
366 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
367 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
368 * @arg DMA1_FLAG_TERR6: DMA1 Channel6 transfer error flag.
369 * @arg DMA1_FLAG_GINT7: DMA1 Channel7 global flag.
370 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
371 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
372 * @arg DMA1_FLAG_TERR7: DMA1 Channel7 transfer error flag.
373
374 * @arg DMA2_FLAG_GINT1: DMA2 Channel 1 global flag.
375 * @arg DMA2_FLAG_TC1: DMA2 Channel 1 transfer complete flag.
376 * @arg DMA2_FLAG_HT1: DMA2 Channel 1 half transfer flag.
377 * @arg DMA2_FLAG_TERR1: DMA2 Channel 1 transfer error flag.
378 * @arg DMA2_FLAG_GINT2: DMA2 Channel 2 global flag.
379 * @arg DMA2_FLAG_TC2: DMA2 Channel 2 transfer complete flag.
380 * @arg DMA2_FLAG_HT2: DMA2 Channel 2 half transfer flag.
381 * @arg DMA2_FLAG_TERR2: DMA2 Channel 2 transfer error flag.
382 * @arg DMA2_FLAG_GINT3: DMA2 Channel 3 global flag.
383 * @arg DMA2_FLAG_TC3: DMA2 Channel 3 transfer complete flag.
384 * @arg DMA2_FLAG_HT3: DMA2 Channel 3 half transfer flag.
385 * @arg DMA2_FLAG_TERR3: DMA2 Channel 3 transfer error flag.
386 * @arg DMA2_FLAG_GINT4: DMA2 Channel 4 global flag.
387 * @arg DMA2_FLAG_TC4: DMA2 Channel 4 transfer complete flag.
388 * @arg DMA2_FLAG_HT4: DMA2 Channel 4 half transfer flag.
389 * @arg DMA2_FLAG_TERR4: DMA2 Channel 4 transfer error flag.
390 * @arg DMA2_FLAG_GINT5: DMA2 Channel 5 global flag.
391 * @arg DMA2_FLAG_TC5: DMA2 Channel 5 transfer complete flag.
392 * @arg DMA2_FLAG_HT5: DMA2 Channel 5 half transfer flag.
393 * @arg DMA2_FLAG_TERR5: DMA2 Channel 5 transfer error flag.
394 *
395 * @retval None
396 *
397 * @note DMA2 Channel only for APM32 High density devices.
398 */
DMA_ClearStatusFlag(uint32_t flag)399 void DMA_ClearStatusFlag(uint32_t flag)
400 {
401 if ((flag & 0x10000000) != RESET)
402 {
403 DMA2->INTFCLR = flag;
404 }
405 else
406 {
407 DMA1->INTFCLR = flag;
408 }
409 }
410
411 /*!
412 * @brief Read whether the specified DMA Channel interrupts is set or not.
413 *
414 * @param interrupt: interrupt source to check.
415 * This parameter can be one of the following values:
416 * @arg DMA1_INT_FLAG_GINT1 : DMA1 Channel 1 global interrupt.
417 * @arg DMA1_INT_FLAG_TC1 : DMA1 Channel 1 transfer complete interrupt.
418 * @arg DMA1_INT_FLAG_HT1 : DMA1 Channel 1 half transfer interrupt.
419 * @arg DMA1_INT_FLAG_TERR1 : DMA1 Channel 1 transfer error interrupt.
420 * @arg DMA1_INT_FLAG_GINT2 : DMA1 Channel2 global interrupt.
421 * @arg DMA1_INT_FLAG_TC2 : DMA1 Channel2 transfer complete interrupt.
422 * @arg DMA1_INT_FLAG_HT2 : DMA1 Channel2 half transfer interrupt.
423 * @arg DMA1_INT_FLAG_TERR2 : DMA1 Channel2 transfer error interrupt.
424 * @arg DMA1_INT_FLAG_GINT3 : DMA1 Channel3 global interrupt.
425 * @arg DMA1_INT_FLAG_TC3 : DMA1 Channel3 transfer complete interrupt.
426 * @arg DMA1_INT_FLAG_HT3 : DMA1 Channel3 half transfer interrupt.
427 * @arg DMA1_INT_FLAG_TERR3 : DMA1 Channel3 transfer error interrupt.
428 * @arg DMA1_INT_FLAG_GINT4 : DMA1 Channel4 global interrupt.
429 * @arg DMA1_INT_FLAG_TC4 : DMA1 Channel4 transfer complete interrupt.
430 * @arg DMA1_INT_FLAG_HT4 : DMA1 Channel4 half transfer interrupt.
431 * @arg DMA1_INT_FLAG_TERR4 : DMA1 Channel4 transfer error interrupt.
432 * @arg DMA1_INT_FLAG_GINT5 : DMA1 Channel5 global interrupt.
433 * @arg DMA1_INT_FLAG_TC5 DMA1 Channel5 transfer complete interrupt.
434 * @arg DMA1_INT_FLAG_HT5 DMA1 Channel5 half transfer interrupt.
435 * @arg DMA1_INT_FLAG_TERR5 : DMA1 Channel5 transfer error interrupt.
436 * @arg DMA1_INT_FLAG_GINT6 : DMA1 Channel6 global interrupt.
437 * @arg DMA1_INT_FLAG_TC6 : DMA1 Channel6 transfer complete interrupt.
438 * @arg DMA1_INT_FLAG_HT6 : DMA1 Channel6 half transfer interrupt.
439 * @arg DMA1_INT_FLAG_TERR6 : DMA1 Channel6 transfer error interrupt.
440 * @arg DMA1_INT_FLAG_GINT7 : DMA1 Channel7 global interrupt.
441 * @arg DMA1_INT_FLAG_TC7 : DMA1 Channel7 transfer complete interrupt.
442 * @arg DMA1_INT_FLAG_HT7 : DMA1 Channel7 half transfer interrupt.
443 * @arg DMA1_INT_FLAG_TERR7 : DMA1 Channel7 transfer error interrupt.
444
445 * @arg DMA2_INT_FLAG_GINT1 : DMA2 Channel 1 global interrupt.
446 * @arg DMA2_INT_FLAG_TC1 : DMA2 Channel 1 transfer complete interrupt.
447 * @arg DMA2_INT_FLAG_HT1 : DMA2 Channel 1 half transfer interrupt.
448 * @arg DMA2_INT_FLAG_TERR1 : DMA2 Channel 1 transfer error interrupt.
449 * @arg DMA2_INT_FLAG_GINT2 : DMA2 Channel 2 global interrupt.
450 * @arg DMA2_INT_FLAG_TC2 : DMA2 Channel 2 transfer complete interrupt.
451 * @arg DMA2_INT_FLAG_HT2 : DMA2 Channel 2 half transfer interrupt.
452 * @arg DMA2_INT_FLAG_TERR2 : DMA2 Channel 2 transfer error interrupt.
453 * @arg DMA2_INT_FLAG_GINT3 : DMA2 Channel 3 global interrupt.
454 * @arg DMA2_INT_FLAG_TC3 : DMA2 Channel 3 transfer complete interrupt.
455 * @arg DMA2_INT_FLAG_HT3 : DMA2 Channel 3 half transfer interrupt.
456 * @arg DMA2_INT_FLAG_TERR3 : DMA2 Channel 3 transfer error interrupt.
457 * @arg DMA2_INT_FLAG_GINT4 : DMA2 Channel 4 global interrupt.
458 * @arg DMA2_INT_FLAG_TC4 : DMA2 Channel 4 transfer complete interrupt.
459 * @arg DMA2_INT_FLAG_HT4 : DMA2 Channel 4 half transfer interrupt.
460 * @arg DMA2_INT_FLAG_TERR4 : DMA2 Channel 4 transfer error interrupt.
461 * @arg DMA2_INT_FLAG_GINT5 : DMA2 Channel 5 global interrupt.
462 * @arg DMA2_INT_FLAG_TC5 : DMA2 Channel 5 transfer complete interrupt.
463 * @arg DMA2_INT_FLAG_HT5 : DMA2 Channel 5 half transfer interrupt.
464 * @arg DMA2_INT_FLAG_TERR5 : DMA2 Channel 5 transfer error interrupt.
465 *
466 * @retval interrupt State
467 *
468 * @note DMA2 Channel only for APM32 High density devices.
469 */
DMA_ReadIntFlag(DMA_INT_FLAG_T flag)470 uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
471 {
472 if ((flag & 0x10000000) != RESET)
473 {
474 if ((DMA2->INTSTS & flag) != RESET)
475 {
476 return SET ;
477 }
478 else
479 {
480 return RESET ;
481 }
482 }
483 else
484 {
485 if ((DMA1->INTSTS & flag) != RESET)
486 {
487 return SET ;
488 }
489 else
490 {
491 return RESET ;
492 }
493 }
494 }
495
496 /*!
497 * @brief Clears the specified DMA Channel's interrupts.
498 *
499 * @param flag: the interrupt flag to Clear.
500 * This parameter can be any combination of the following values:
501 * @arg DMA1_INT_FLAG_GINT1 : DMA1 Channel 1 global interrupt.
502 * @arg DMA1_INT_FLAG_TC1 : DMA1 Channel 1 transfer complete interrupt.
503 * @arg DMA1_INT_FLAG_HT1 : DMA1 Channel 1 half transfer interrupt.
504 * @arg DMA1_INT_FLAG_TERR1 : DMA1 Channel 1 transfer error interrupt.
505 * @arg DMA1_INT_FLAG_GINT2 : DMA1 Channel2 global interrupt.
506 * @arg DMA1_INT_FLAG_TC2 : DMA1 Channel2 transfer complete interrupt.
507 * @arg DMA1_INT_FLAG_HT2 : DMA1 Channel2 half transfer interrupt.
508 * @arg DMA1_INT_FLAG_TERR2 : DMA1 Channel2 transfer error interrupt.
509 * @arg DMA1_INT_FLAG_GINT3 : DMA1 Channel3 global interrupt.
510 * @arg DMA1_INT_FLAG_TC3 : DMA1 Channel3 transfer complete interrupt.
511 * @arg DMA1_INT_FLAG_HT3 : DMA1 Channel3 half transfer interrupt.
512 * @arg DMA1_INT_FLAG_TERR3 : DMA1 Channel3 transfer error interrupt.
513 * @arg DMA1_INT_FLAG_GINT4 : DMA1 Channel4 global interrupt.
514 * @arg DMA1_INT_FLAG_TC4 : DMA1 Channel4 transfer complete interrupt.
515 * @arg DMA1_INT_FLAG_HT4 : DMA1 Channel4 half transfer interrupt.
516 * @arg DMA1_INT_FLAG_TERR4 : DMA1 Channel4 transfer error interrupt.
517 * @arg DMA1_INT_FLAG_GINT5 : DMA1 Channel5 global interrupt.
518 * @arg DMA1_INT_FLAG_TC5 DMA1 Channel5 transfer complete interrupt.
519 * @arg DMA1_INT_FLAG_HT5 DMA1 Channel5 half transfer interrupt.
520 * @arg DMA1_INT_FLAG_TERR5 : DMA1 Channel5 transfer error interrupt.
521 * @arg DMA1_INT_FLAG_GINT6 : DMA1 Channel6 global interrupt.
522 * @arg DMA1_INT_FLAG_TC6 : DMA1 Channel6 transfer complete interrupt.
523 * @arg DMA1_INT_FLAG_HT6 : DMA1 Channel6 half transfer interrupt.
524 * @arg DMA1_INT_FLAG_TERR6 : DMA1 Channel6 transfer error interrupt.
525 * @arg DMA1_INT_FLAG_GINT7 : DMA1 Channel7 global interrupt.
526 * @arg DMA1_INT_FLAG_TC7 : DMA1 Channel7 transfer complete interrupt.
527 * @arg DMA1_INT_FLAG_HT7 : DMA1 Channel7 half transfer interrupt.
528 * @arg DMA1_INT_FLAG_TERR7 : DMA1 Channel7 transfer error interrupt.
529
530 * @arg DMA2_INT_FLAG_GINT1 : DMA2 Channel 1 global interrupt.
531 * @arg DMA2_INT_FLAG_TC1 : DMA2 Channel 1 transfer complete interrupt.
532 * @arg DMA2_INT_FLAG_HT1 : DMA2 Channel 1 half transfer interrupt.
533 * @arg DMA2_INT_FLAG_TERR1 : DMA2 Channel 1 transfer error interrupt.
534 * @arg DMA2_INT_FLAG_GINT2 : DMA2 Channel 2 global interrupt.
535 * @arg DMA2_INT_FLAG_TC2 : DMA2 Channel 2 transfer complete interrupt.
536 * @arg DMA2_INT_FLAG_HT2 : DMA2 Channel 2 half transfer interrupt.
537 * @arg DMA2_INT_FLAG_TERR2 : DMA2 Channel 2 transfer error interrupt.
538 * @arg DMA2_INT_FLAG_GINT3 : DMA2 Channel 3 global interrupt.
539 * @arg DMA2_INT_FLAG_TC3 : DMA2 Channel 3 transfer complete interrupt.
540 * @arg DMA2_INT_FLAG_HT3 : DMA2 Channel 3 half transfer interrupt.
541 * @arg DMA2_INT_FLAG_TERR3 : DMA2 Channel 3 transfer error interrupt.
542 * @arg DMA2_INT_FLAG_GINT4 : DMA2 Channel 4 global interrupt.
543 * @arg DMA2_INT_FLAG_TC4 : DMA2 Channel 4 transfer complete interrupt.
544 * @arg DMA2_INT_FLAG_HT4 : DMA2 Channel 4 half transfer interrupt.
545 * @arg DMA2_INT_FLAG_TERR4 : DMA2 Channel 4 transfer error interrupt.
546 * @arg DMA2_INT_FLAG_GINT5 : DMA2 Channel 5 global interrupt.
547 * @arg DMA2_INT_FLAG_TC5 : DMA2 Channel 5 transfer complete interrupt.
548 * @arg DMA2_INT_FLAG_HT5 : DMA2 Channel 5 half transfer interrupt.
549 * @arg DMA2_INT_FLAG_TERR5 : DMA2 Channel 5 transfer error interrupt.
550 *
551 * @retval None
552 *
553 * @note DMA2 Channel only for APM32 High density devices.
554 */
DMA_ClearIntFlag(uint32_t flag)555 void DMA_ClearIntFlag(uint32_t flag)
556 {
557 if ((flag & 0x10000000) != RESET)
558 {
559 DMA2->INTFCLR = flag;
560 }
561 else
562 {
563 DMA1->INTFCLR = flag;
564 }
565 }
566
567 /**@} end of group DMA_Functions*/
568 /**@} end of group DMA_Driver*/
569 /**@} end of group APM32F10x_StdPeriphDriver */
570