1 /*!
2  * @file        apm32f10x_dma.h
3  *
4  * @brief       This file contains all the functions prototypes for the DMA firmware library
5  *
6  * @version     V1.0.4
7  *
8  * @date        2022-12-01
9  *
10  * @attention
11  *
12  *  Copyright (C) 2020-2022 Geehy Semiconductor
13  *
14  *  You may not use this file except in compliance with the
15  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16  *
17  *  The program is only for reference, which is distributed in the hope
18  *  that it will be useful and instructional for customers to develop
19  *  their software. Unless required by applicable law or agreed to in
20  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23  *  and limitations under the License.
24  */
25 
26 #ifndef __APM32F10X_DMA_H
27 #define __APM32F10X_DMA_H
28 
29 /* Includes */
30 #include "apm32f10x.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 /** @addtogroup APM32F10x_StdPeriphDriver
37   @{
38 */
39 
40 /** @addtogroup DMA_Driver DMA Driver
41   @{
42 */
43 
44 /** @defgroup DMA_Enumerations Enumerations
45   @{
46 */
47 
48 /**
49  * @brief   DMA Transmission direction
50  */
51 typedef enum
52 {
53     DMA_DIR_PERIPHERAL_SRC,
54     DMA_DIR_PERIPHERAL_DST
55 } DMA_DIR_T;
56 
57 /**
58  * @brief   DMA Peripheral address increment
59  */
60 typedef enum
61 {
62     DMA_PERIPHERAL_INC_DISABLE,
63     DMA_PERIPHERAL_INC_ENABLE
64 } DMA_PERIPHERAL_INC_T;
65 
66 /**
67  * @brief   DMA Memory address increment
68  */
69 typedef enum
70 {
71     DMA_MEMORY_INC_DISABLE,
72     DMA_MEMORY_INC_ENABLE
73 } DMA_MEMORY_INC_T;
74 
75 /**
76  * @brief   DMA Peripheral Data Size
77  */
78 typedef enum
79 {
80     DMA_PERIPHERAL_DATA_SIZE_BYTE,
81     DMA_PERIPHERAL_DATA_SIZE_HALFWORD,
82     DMA_PERIPHERAL_DATA_SIZE_WOED
83 } DMA_PERIPHERAL_DATA_SIZE_T;
84 
85 /**
86  * @brief   DMA Memory Data Size
87  */
88 typedef enum
89 {
90     DMA_MEMORY_DATA_SIZE_BYTE,
91     DMA_MEMORY_DATA_SIZE_HALFWORD,
92     DMA_MEMORY_DATA_SIZE_WOED
93 } DMA_MEMORY_DATA_SIZE_T;
94 
95 /**
96  * @brief   DMA Mode
97  */
98 typedef enum
99 {
100     DMA_MODE_NORMAL,
101     DMA_MODE_CIRCULAR
102 } DMA_LOOP_MODE_T;
103 
104 /**
105  * @brief   DMA priority level
106  */
107 typedef enum
108 {
109     DMA_PRIORITY_LOW,
110     DMA_PRIORITY_MEDIUM,
111     DMA_PRIORITY_HIGH,
112     DMA_PRIORITY_VERYHIGH
113 } DMA_PRIORITY_T;
114 
115 /**
116  * @brief   DMA Memory to Memory
117  */
118 typedef enum
119 {
120     DMA_M2MEN_DISABLE,
121     DMA_M2MEN_ENABLE
122 } DMA_M2MEN_T;
123 
124 /**
125  * @brief   DMA interrupt
126  */
127 typedef enum
128 {
129     DMA_INT_TC   = 0x00000002,
130     DMA_INT_HT   = 0x00000004,
131     DMA_INT_TERR = 0x00000008
132 } DMA_INT_T;
133 
134 /**
135  * @brief   DMA Flag
136  */
137 typedef enum
138 {
139     DMA1_FLAG_GINT1 = 0x00000001,
140     DMA1_FLAG_TC1   = 0x00000002,
141     DMA1_FLAG_HT1   = 0x00000004,
142     DMA1_FLAG_TERR1 = 0x00000008,
143     DMA1_FLAG_GINT2 = 0x00000010,
144     DMA1_FLAG_TC2   = 0x00000020,
145     DMA1_FLAG_HT2   = 0x00000040,
146     DMA1_FLAG_TERR2 = 0x00000080,
147     DMA1_FLAG_GINT3 = 0x00000100,
148     DMA1_FLAG_TC3   = 0x00000200,
149     DMA1_FLAG_HT3   = 0x00000400,
150     DMA1_FLAG_TERR3 = 0x00000800,
151     DMA1_FLAG_GINT4 = 0x00001000,
152     DMA1_FLAG_TC4   = 0x00002000,
153     DMA1_FLAG_HT4   = 0x00004000,
154     DMA1_FLAG_TERR4 = 0x00008000,
155     DMA1_FLAG_GINT5 = 0x00010000,
156     DMA1_FLAG_TC5   = 0x00020000,
157     DMA1_FLAG_HT5   = 0x00040000,
158     DMA1_FLAG_TERR5 = 0x00080000,
159     DMA1_FLAG_GINT6 = 0x00100000,
160     DMA1_FLAG_TC6   = 0x00200000,
161     DMA1_FLAG_HT6   = 0x00400000,
162     DMA1_FLAG_TERR6 = 0x00800000,
163     DMA1_FLAG_GINT7 = 0x01000000,
164     DMA1_FLAG_TC7   = 0x02000000,
165     DMA1_FLAG_HT7   = 0x04000000,
166     DMA1_FLAG_TERR7 = 0x08000000,
167 
168     DMA2_FLAG_GINT1 = 0x10000001,
169     DMA2_FLAG_TC1   = 0x10000002,
170     DMA2_FLAG_HT1   = 0x10000004,
171     DMA2_FLAG_TERR1 = 0x10000008,
172     DMA2_FLAG_GINT2 = 0x10000010,
173     DMA2_FLAG_TC2   = 0x10000020,
174     DMA2_FLAG_HT2   = 0x10000040,
175     DMA2_FLAG_TERR2 = 0x10000080,
176     DMA2_FLAG_GINT3 = 0x10000100,
177     DMA2_FLAG_TC3   = 0x10000200,
178     DMA2_FLAG_HT3   = 0x10000400,
179     DMA2_FLAG_TERR3 = 0x10000800,
180     DMA2_FLAG_GINT4 = 0x10001000,
181     DMA2_FLAG_TC4   = 0x10002000,
182     DMA2_FLAG_HT4   = 0x10004000,
183     DMA2_FLAG_TERR4 = 0x10008000,
184     DMA2_FLAG_GINT5 = 0x10010000,
185     DMA2_FLAG_TC5   = 0x10020000,
186     DMA2_FLAG_HT5   = 0x10040000,
187     DMA2_FLAG_TERR5 = 0x10080000
188 } DMA_FLAG_T;
189 
190 /**
191  * @brief DMA Interrupt Flag
192  */
193 typedef enum
194 {
195     DMA1_INT_FLAG_GINT1   = 0x00000001,
196     DMA1_INT_FLAG_TC1     = 0x00000002,
197     DMA1_INT_FLAG_HT1     = 0x00000004,
198     DMA1_INT_FLAG_TERR1   = 0x00000008,
199     DMA1_INT_FLAG_GINT2   = 0x00000010,
200     DMA1_INT_FLAG_TC2     = 0x00000020,
201     DMA1_INT_FLAG_HT2     = 0x00000040,
202     DMA1_INT_FLAG_TERR2   = 0x00000080,
203     DMA1_INT_FLAG_GINT3   = 0x00000100,
204     DMA1_INT_FLAG_TC3     = 0x00000200,
205     DMA1_INT_FLAG_HT3     = 0x00000400,
206     DMA1_INT_FLAG_TERR3   = 0x00000800,
207     DMA1_INT_FLAG_GINT4   = 0x00001000,
208     DMA1_INT_FLAG_TC4     = 0x00002000,
209     DMA1_INT_FLAG_HT4     = 0x00004000,
210     DMA1_INT_FLAG_TERR4   = 0x00008000,
211     DMA1_INT_FLAG_GINT5   = 0x00010000,
212     DMA1_INT_FLAG_TC5     = 0x00020000,
213     DMA1_INT_FLAG_HT5     = 0x00040000,
214     DMA1_INT_FLAG_TERR5   = 0x00080000,
215     DMA1_INT_FLAG_GINT6   = 0x00100000,
216     DMA1_INT_FLAG_TC6     = 0x00200000,
217     DMA1_INT_FLAG_HT6     = 0x00400000,
218     DMA1_INT_FLAG_TERR6   = 0x00800000,
219     DMA1_INT_FLAG_GINT7   = 0x01000000,
220     DMA1_INT_FLAG_TC7     = 0x02000000,
221     DMA1_INT_FLAG_HT7     = 0x04000000,
222     DMA1_INT_FLAG_TERR7   = 0x08000000,
223 
224     DMA2_INT_FLAG_GINT1   = 0x10000001,
225     DMA2_INT_FLAG_TC1     = 0x10000002,
226     DMA2_INT_FLAG_HT1     = 0x10000004,
227     DMA2_INT_FLAG_TERR1   = 0x10000008,
228     DMA2_INT_FLAG_GINT2   = 0x10000010,
229     DMA2_INT_FLAG_TC2     = 0x10000020,
230     DMA2_INT_FLAG_HT2     = 0x10000040,
231     DMA2_INT_FLAG_TERR2   = 0x10000080,
232     DMA2_INT_FLAG_GINT3   = 0x10000100,
233     DMA2_INT_FLAG_TC3     = 0x10000200,
234     DMA2_INT_FLAG_HT3     = 0x10000400,
235     DMA2_INT_FLAG_TERR3   = 0x10000800,
236     DMA2_INT_FLAG_GINT4   = 0x10001000,
237     DMA2_INT_FLAG_TC4     = 0x10002000,
238     DMA2_INT_FLAG_HT4     = 0x10004000,
239     DMA2_INT_FLAG_TERR4   = 0x10008000,
240     DMA2_INT_FLAG_GINT5   = 0x10010000,
241     DMA2_INT_FLAG_TC5     = 0x10020000,
242     DMA2_INT_FLAG_HT5     = 0x10040000,
243     DMA2_INT_FLAG_TERR5   = 0x10080000
244 } DMA_INT_FLAG_T;
245 
246 /**@} end of group DMA_Enumerations*/
247 
248 
249 /** @defgroup DMA_Structures Structures
250   @{
251 */
252 
253 /**
254  * @brief    DMA Config struct definition
255  */
256 typedef struct
257 {
258     uint32_t                   peripheralBaseAddr;
259     uint32_t                   memoryBaseAddr;
260     DMA_DIR_T                  dir;
261     uint32_t                   bufferSize;
262     DMA_PERIPHERAL_INC_T       peripheralInc;
263     DMA_MEMORY_INC_T           memoryInc;
264     DMA_PERIPHERAL_DATA_SIZE_T peripheralDataSize;
265     DMA_MEMORY_DATA_SIZE_T     memoryDataSize;
266     DMA_LOOP_MODE_T            loopMode;
267     DMA_PRIORITY_T             priority;
268     DMA_M2MEN_T                M2M;
269 } DMA_Config_T;
270 
271 /**@} end of group DMA_Structures*/
272 
273 
274 /** @defgroup DMA_Functions Functions
275   @{
276 */
277 
278 /* Reset and configuration */
279 void DMA_Reset(DMA_Channel_T* channel);
280 void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig);
281 void DMA_ConfigStructInit(DMA_Config_T* dmaConfig);
282 void DMA_Enable(DMA_Channel_T* channel);
283 void DMA_Disable(DMA_Channel_T* channel);
284 
285 /* Data number */
286 void DMA_ConfigDataNumber(DMA_Channel_T* channel, uint16_t dataNumber);
287 uint16_t DMA_ReadDataNumber(DMA_Channel_T* channel);
288 
289 /* Interrupt and flag */
290 void DMA_EnableInterrupt(DMA_Channel_T* channel, uint32_t interrupt);
291 void DMA_DisableInterrupt(DMA_Channel_T* channel, uint32_t interrupt);
292 uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag);
293 void DMA_ClearStatusFlag(uint32_t flag);
294 uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag);
295 void DMA_ClearIntFlag(uint32_t flag);
296 
297 /**@} end of group DMA_Functions*/
298 /**@} end of group DMA_Driver */
299 /**@} end of group APM32F10x_StdPeriphDriver */
300 
301 #ifdef __cplusplus
302 }
303 #endif
304 
305 #endif /* __APM32F10X_DMA_H */
306