1 /*!
2  * @file        apm32f10x_tmr.h
3  *
4  * @brief       This file contains all the functions prototypes for the TMR firmware library.
5  *
6  * @version     V1.0.4
7  *
8  * @date        2022-12-01
9  *
10  * @attention
11  *
12  *  Copyright (C) 2020-2022 Geehy Semiconductor
13  *
14  *  You may not use this file except in compliance with the
15  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16  *
17  *  The program is only for reference, which is distributed in the hope
18  *  that it will be useful and instructional for customers to develop
19  *  their software. Unless required by applicable law or agreed to in
20  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23  *  and limitations under the License.
24  */
25 /* Define to prevent recursive inclusion */
26 #ifndef __APM32F10X_TMR_H
27 #define __APM32F10X_TMR_H
28 
29 /* Includes */
30 #include "apm32f10x.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 /** @addtogroup APM32F10x_StdPeriphDriver
37   @{
38 */
39 
40 /** @addtogroup TMR_Driver TMR Driver
41   @{
42 */
43 
44 /** @defgroup TMR_Enumerations Enumerations
45   @{
46 */
47 
48 /**
49  * @brief TMR Counter Mode
50  */
51 typedef enum
52 {
53     TMR_COUNTER_MODE_UP             = 0x0000,
54     TMR_COUNTER_MODE_DOWN           = 0x0010,
55     TMR_COUNTER_MODE_CENTERALIGNED1 = 0x0020,
56     TMR_COUNTER_MODE_CENTERALIGNED2 = 0x0040,
57     TMR_COUNTER_MODE_CENTERALIGNED3 = 0x0060
58 } TMR_COUNTER_MODE_T;
59 
60 /**
61  * @brief TMR Clock division
62  */
63 typedef enum
64 {
65     TMR_CLOCK_DIV_1,
66     TMR_CLOCK_DIV_2,
67     TMR_CLOCK_DIV_4
68 } TMR_CLOCK_DIV_T;
69 
70 /**
71  * @brief TMR Output Compare and PWM modes
72  */
73 typedef enum
74 {
75     TMR_OC_MODE_TMRING     = 0x00,
76     TMR_OC_MODE_ACTIVE     = 0x01,
77     TMR_OC_MODE_INACTIVE   = 0x02,
78     TMR_OC_MODE_TOGGEL     = 0x03,
79     TMR_OC_MODE_LOWLEVEL   = 0x04,
80     TMR_OC_MODE_HIGHLEVEL  = 0x05,
81     TMR_OC_MODE_PWM1       = 0x06,
82     TMR_OC_MODE_PWM2       = 0x07
83 } TMR_OC_MODE_T;
84 
85 /**
86  * @brief TMR Output Compare state
87  */
88 typedef enum
89 {
90     TMR_OC_STATE_DISABLE,
91     TMR_OC_STATE_ENABLE
92 } TMR_OC_STATE_T;
93 
94 /**
95  * @brief TMR Output Compare N state
96  */
97 typedef enum
98 {
99     TMR_OC_NSTATE_DISABLE,
100     TMR_OC_NSTATE_ENABLE
101 } TMR_OC_NSTATE_T;
102 
103 /**
104  * @brief TMR Output Compare Polarity
105  */
106 typedef enum
107 {
108     TMR_OC_POLARITY_HIGH,
109     TMR_OC_POLARITY_LOW
110 } TMR_OC_POLARITY_T;
111 
112 /**
113  * @brief TMR Output Compare N Polarity
114  */
115 typedef enum
116 {
117     TMR_OC_NPOLARITY_HIGH,
118     TMR_OC_NPOLARITY_LOW
119 } TMR_OC_NPOLARITY_T;
120 
121 /**
122  * @brief TMR Output Compare Idle State
123  */
124 typedef enum
125 {
126     TMR_OC_IDLE_STATE_RESET,
127     TMR_OC_IDLE_STATE_SET
128 } TMR_OC_IDLE_STATE_T;
129 
130 /**
131  * @brief TMR Output Compare N Idle State
132  */
133 typedef enum
134 {
135     TMR_OC_NIDLE_STATE_RESET,
136     TMR_OC_NIDLE_STATE_SET
137 } TMR_OC_NIDLE_STATE_T;
138 
139 /**
140  * @brief TMR Input Capture Init structure definition
141  */
142 typedef enum
143 {
144     TMR_CHANNEL_1 = 0x0000,
145     TMR_CHANNEL_2 = 0x0004,
146     TMR_CHANNEL_3 = 0x0008,
147     TMR_CHANNEL_4 = 0x000C
148 } TMR_CHANNEL_T;
149 
150 /**
151  * @brief TMR Input Capture Polarity
152  */
153 typedef enum
154 {
155     TMR_IC_POLARITY_RISING   = 0x00,
156     TMR_IC_POLARITY_FALLING  = 0x02,
157     TMR_IC_POLARITY_BOTHEDGE = 0x0A
158 } TMR_IC_POLARITY_T;
159 
160 /**
161  * @brief TMR Input Capture Selection
162  */
163 typedef enum
164 {
165     TMR_IC_SELECTION_DIRECT_TI   = 0x01,
166     TMR_IC_SELECTION_INDIRECT_TI = 0x02,
167     TMR_IC_SELECTION_TRC         = 0x03
168 } TMR_IC_SELECTION_T;
169 
170 /**
171  * @brief TMR Input Capture Prescaler
172  */
173 typedef enum
174 {
175     TMR_IC_PSC_1,
176     TMR_IC_PSC_2,
177     TMR_IC_PSC_4,
178     TMR_IC_PSC_8
179 } TMR_IC_PSC_T;
180 
181 /**
182  * @brief TMR Specifies the Off-State selection used in Run mode
183  */
184 typedef enum
185 {
186     TMR_RMOS_STATE_DISABLE,
187     TMR_RMOS_STATE_ENABLE
188 } TMR_RMOS_STATE_T;
189 
190 /**
191  * @brief TMR Closed state configuration in idle mode
192  */
193 typedef enum
194 {
195     TMR_IMOS_STATE_DISABLE,
196     TMR_IMOS_STATE_ENABLE
197 } TMR_IMOS_STATE_T;
198 
199 /**
200  * @brief TMR Protect mode configuration values
201  */
202 typedef enum
203 {
204     TMR_LOCK_LEVEL_OFF,
205     TMR_LOCK_LEVEL_1,
206     TMR_LOCK_LEVEL_2,
207     TMR_LOCK_LEVEL_3
208 } TMR_LOCK_LEVEL_T;
209 
210 /**
211  * @brief TMR BRK state
212  */
213 typedef enum
214 {
215     TMR_BRK_STATE_DISABLE,
216     TMR_BRK_STATE_ENABLE
217 } TMR_BRK_STATE_T;
218 
219 /**
220  * @brief TMR Specifies the Break Input pin polarity.
221  */
222 typedef enum
223 {
224     TMR_BRK_POLARITY_LOW,
225     TMR_BRK_POLARITY_HIGH
226 } TMR_BRK_POLARITY_T;
227 
228 /**
229  * @brief TMR Specifies the Break Input pin polarity.
230  */
231 typedef enum
232 {
233     TMR_AUTOMATIC_OUTPUT_DISABLE,
234     TMR_AUTOMATIC_OUTPUT_ENABLE
235 } TMR_AUTOMATIC_OUTPUT_T;
236 
237 /**
238  * @brief    TMR_interrupt_sources
239  */
240 typedef enum
241 {
242     TMR_INT_UPDATE = 0x0001,
243     TMR_INT_CC1    = 0x0002,
244     TMR_INT_CC2    = 0x0004,
245     TMR_INT_CC3    = 0x0008,
246     TMR_INT_CC4    = 0x0010,
247     TMR_INT_COM    = 0x0020,
248     TMR_INT_TRG    = 0x0040,
249     TMR_INT_BRK    = 0x0080
250 } TMR_INT_T;
251 
252 /**
253  * @brief    TMR event sources
254  */
255 typedef enum
256 {
257     TMR_EVENT_UPDATE = 0x001,
258     TMR_EVENT_CC1    = 0x002,
259     TMR_EVENT_CC2    = 0x004,
260     TMR_EVENT_CC3    = 0x008,
261     TMR_EVENT_CC4    = 0x010,
262     TMR_EVENT_COM    = 0x020,
263     TMR_EVENT_TRG    = 0x040,
264     TMR_EVENT_BRK    = 0x080
265 } TMR_EVENT_T;
266 
267 /**
268  * @brief    TMR DMA Base Address
269  */
270 typedef enum
271 {
272     TMR_DMA_BASE_CTRL1   = 0x0000,
273     TMR_DMA_BASE_CTRL2   = 0x0001,
274     TMR_DMA_BASE_SMCTRL  = 0x0002,
275     TMR_DMA_BASE_DIEN    = 0x0003,
276     TMR_DMA_BASE_STS     = 0x0004,
277     TMR_DMA_BASE_CEG     = 0x0005,
278     TMR_DMA_BASE_CCM1    = 0x0006,
279     TMR_DMA_BASE_CCM2    = 0x0007,
280     TMR_DMA_BASE_CCEN    = 0x0008,
281     TMR_DMA_BASE_CNT     = 0x0009,
282     TMR_DMA_BASE_PSC     = 0x000A,
283     TMR_DMA_BASE_AUTORLD = 0x000B,
284     TMR_DMA_BASE_REPCNT  = 0x000C,
285     TMR_DMA_BASE_CC1     = 0x000D,
286     TMR_DMA_BASE_CC2     = 0x000E,
287     TMR_DMA_BASE_CC3     = 0x000F,
288     TMR_DMA_BASE_CC4     = 0x0010,
289     TMR_DMA_BASE_BDT     = 0x0011,
290     TMR_DMA_BASE_DCTRL   = 0x0012
291 } TMR_DMA_BASE_T;
292 
293 /**
294  * @brief    TMR DMA Burst Length
295  */
296 typedef enum
297 {
298     TMR_DMA_BURSTLENGTH_1TRANSFER   = 0x0000,
299     TMR_DMA_BURSTLENGTH_2TRANSFERS  = 0x0100,
300     TMR_DMA_BURSTLENGTH_3TRANSFERS  = 0x0200,
301     TMR_DMA_BURSTLENGTH_4TRANSFERS  = 0x0300,
302     TMR_DMA_BURSTLENGTH_5TRANSFERS  = 0x0400,
303     TMR_DMA_BURSTLENGTH_6TRANSFERS  = 0x0500,
304     TMR_DMA_BURSTLENGTH_7TRANSFERS  = 0x0600,
305     TMR_DMA_BURSTLENGTH_8TRANSFERS  = 0x0700,
306     TMR_DMA_BURSTLENGTH_9TRANSFERS  = 0x0800,
307     TMR_DMA_BURSTLENGTH_10TRANSFERS = 0x0900,
308     TMR_DMA_BURSTLENGTH_11TRANSFERS = 0x0A00,
309     TMR_DMA_BURSTLENGTH_12TRANSFERS = 0x0B00,
310     TMR_DMA_BURSTLENGTH_13TRANSFERS = 0x0C00,
311     TMR_DMA_BURSTLENGTH_14TRANSFERS = 0x0D00,
312     TMR_DMA_BURSTLENGTH_15TRANSFERS = 0x0E00,
313     TMR_DMA_BURSTLENGTH_16TRANSFERS = 0x0F00,
314     TMR_DMA_BURSTLENGTH_17TRANSFERS = 0x1000,
315     TMR_DMA_BURSTLENGTH_18TRANSFERS = 0x1100,
316 } TMR_DMA_BURSTLENGTH_T;
317 
318 /**
319  * @brief    TMR DMA Soueces
320  */
321 typedef enum
322 {
323     TMR_DMA_SOURCE_UPDATE    = 0x0100,
324     TMR_DMA_SOURCE_CC1       = 0x0200,
325     TMR_DMA_SOURCE_CC2       = 0x0400,
326     TMR_DMA_SOURCE_CC3       = 0x0800,
327     TMR_DMA_SOURCE_CC4       = 0x1000,
328     TMR_DMA_SOURCE_COM       = 0x2000,
329     TMR_DMA_SOURCE_TRG       = 0x4000
330 } TMR_DMA_SOURCE_T;
331 
332 /**
333  * @brief    TMR Internal Trigger Selection
334  */
335 typedef enum
336 {
337     TMR_TRIGGER_SOURCE_ITR0     = 0x00,
338     TMR_TRIGGER_SOURCE_ITR1     = 0x01,
339     TMR_TRIGGER_SOURCE_ITR2     = 0x02,
340     TMR_TRIGGER_SOURCE_ITR3     = 0x03,
341     TMR_TRIGGER_SOURCE_TI1F_ED  = 0x04,
342     TMR_TRIGGER_SOURCE_TI1FP1   = 0x05,
343     TMR_TRIGGER_SOURCE_TI2FP2   = 0x06,
344     TMR_TRIGGER_SOURCE_ETRF     = 0x07
345 } TMR_TRIGGER_SOURCE_T;
346 
347 /**
348  * @brief    TMR  The external Trigger Prescaler.
349  */
350 typedef enum
351 {
352     TMR_EXTTRG_PSC_OFF   = 0x00,
353     TMR_EXTTRG_PSC_DIV2  = 0x01,
354     TMR_EXTTRG_PSC_DIV4  = 0x02,
355     TMR_EXTTRG_PSC_DIV8  = 0x03
356 } TMR_EXTTRG_PSC_T;
357 
358 /**
359  * @brief    TMR External Trigger Polarity
360  */
361 typedef enum
362 {
363     TMR_EXTTGR_POL_NONINVERTED,
364     TMR_EXTTRG_POL_INVERTED
365 } TMR_EXTTRG_POL_T;
366 
367 /**
368  * @brief    TMR Prescaler Reload Mode
369  */
370 typedef enum
371 {
372     TMR_PSC_RELOAD_UPDATE,
373     TMR_PSC_RELOAD_IMMEDIATE
374 } TMR_PSC_RELOAD_T;
375 
376 /**
377  * @brief    TMR Encoder Mode
378  */
379 typedef enum
380 {
381     TMR_ENCODER_MODE_TI1      = 0x01,
382     TMR_ENCODER_MODE_TI2      = 0x02,
383     TMR_ENCODER_MODE_TI12     = 0x03
384 } TMR_ENCODER_MODE_T;
385 
386 /**
387  * @brief    TMR Forced Action
388  */
389 typedef enum
390 {
391     TMR_FORCED_ACTION_INACTIVE = 0x04,
392     TMR_FORCED_ACTION_ACTIVE   = 0x05
393 } TMR_FORCED_ACTION_T;
394 
395 /**
396  * @brief    TMR Output Compare Preload State
397  */
398 typedef enum
399 {
400     TMR_OC_PRELOAD_DISABLE,
401     TMR_OC_PRELOAD_ENABLE
402 } TMR_OC_PRELOAD_T;
403 
404 /**
405  * @brief    TMR Output Compare Preload State
406  */
407 typedef enum
408 {
409     TMR_OC_FAST_DISABLE,
410     TMR_OC_FAST_ENABLE
411 } TMR_OC_FAST_T;
412 
413 /**
414  * @brief    TMR Output Compare Preload State
415  */
416 typedef enum
417 {
418     TMR_OC_CLEAR_DISABLE,
419     TMR_OC_CLEAR_ENABLE
420 } TMR_OC_CLEAR_T;
421 
422 /**
423  * @brief    TMR UpdateSource
424  */
425 typedef enum
426 {
427     TMR_UPDATE_SOURCE_GLOBAL,
428     TMR_UPDATE_SOURCE_REGULAR,
429 } TMR_UPDATE_SOURCE_T;
430 
431 /**
432  * @brief    TMR Single Pulse Mode
433  */
434 typedef enum
435 {
436     TMR_SPM_REPETITIVE,
437     TMR_SPM_SINGLE,
438 } TMR_SPM_T;
439 
440 /**
441  * @brief    TMR Trigger Output Source
442  */
443 typedef enum
444 {
445     TMR_TRGO_SOURCE_RESET,
446     TMR_TRGO_SOURCE_ENABLE,
447     TMR_TRGO_SOURCE_UPDATE,
448     TMR_TRGO_SOURCE_OC1,
449     TMR_TRGO_SOURCE_OC1REF,
450     TMR_TRGO_SOURCE_OC2REF,
451     TMR_TRGO_SOURCE_OC3REF,
452     TMR_TRGO_SOURCE_OC4REF
453 } TMR_TRGO_SOURCE_T;
454 
455 /**
456  * @brief    TMR Slave Mode
457  */
458 typedef enum
459 {
460     TMR_SLAVE_MODE_RESET     = 0x04,
461     TMR_SLAVE_MODE_GATED     = 0x05,
462     TMR_SLAVE_MODE_TRIGGER   = 0x06,
463     TMR_SLAVE_MODE_EXTERNAL1 = 0x07
464 } TMR_SLAVE_MODE_T;
465 
466 /**
467  * @brief    TMR Flag
468  */
469 typedef enum
470 {
471     TMR_FLAG_UPDATE  = 0x0001,
472     TMR_FLAG_CC1     = 0x0002,
473     TMR_FLAG_CC2     = 0x0004,
474     TMR_FLAG_CC3     = 0x0008,
475     TMR_FLAG_CC4     = 0x0010,
476     TMR_FLAG_COM     = 0x0020,
477     TMR_FLAG_TRG     = 0x0040,
478     TMR_FLAG_BRK     = 0x0080,
479     TMR_FLAG_CC1RC   = 0x0200,
480     TMR_FLAG_CC2RC   = 0x0400,
481     TMR_FLAG_CC3RC   = 0x0800,
482     TMR_FLAG_CC4RC   = 0x1000
483 } TMR_FLAG_T;
484 
485 /**@} end of group TMR_Enumerations */
486 
487 /** @defgroup TMR_Structures Structures
488   @{
489 */
490 
491 /**
492  * @brief    TMR Base Configure structure definition
493  */
494 typedef struct
495 {
496     TMR_COUNTER_MODE_T     countMode;
497     TMR_CLOCK_DIV_T        clockDivision;
498     uint16_t               period;            /*!< This must between 0x0000 and 0xFFFF */
499     uint16_t               division;          /*!< This must between 0x0000 and 0xFFFF */
500     uint8_t                repetitionCounter; /*!< This must between 0x00 and 0xFF, only for TMR1 and TMR8. */
501 } TMR_BaseConfig_T; ;
502 
503 /**
504  * @brief    TMR Output Compare Configure structure definition
505  */
506 typedef struct
507 {
508     TMR_OC_MODE_T          mode;
509     TMR_OC_STATE_T         outputState;
510     TMR_OC_NSTATE_T        outputNState;
511     TMR_OC_POLARITY_T      polarity;
512     TMR_OC_NPOLARITY_T     nPolarity;
513     TMR_OC_IDLE_STATE_T    idleState;
514     TMR_OC_NIDLE_STATE_T   nIdleState;
515     uint16_t               pulse;     /*!< This must between 0x0000 and 0xFFFF */
516 } TMR_OCConfig_T;
517 
518 /**
519  * @brief    TMR BDT structure definition
520  */
521 typedef struct
522 {
523     TMR_RMOS_STATE_T       RMOS;
524     TMR_IMOS_STATE_T       IMOS;
525     TMR_LOCK_LEVEL_T       lockLevel;
526     uint16_t               deadTime;
527     TMR_BRK_STATE_T        BRKState;
528     TMR_BRK_POLARITY_T     BRKPolarity;
529     TMR_AUTOMATIC_OUTPUT_T automaticOutput;
530 } TMR_BDTConfig_T;
531 
532 /**
533  * @brief    TMR Input Capture Configure structure definition
534  */
535 typedef struct
536 {
537     TMR_CHANNEL_T          channel;
538     TMR_IC_POLARITY_T      polarity;
539     TMR_IC_SELECTION_T     selection;
540     TMR_IC_PSC_T           prescaler;
541     uint16_t               filter;    /*!< This must between 0x00 and 0x0F */
542 } TMR_ICConfig_T;
543 
544 /**@} end of group TMR_Structures */
545 
546 /** @defgroup  TMR_Functions Functions
547   @{
548 */
549 
550 /* Reset and Configuration */
551 void TMR_Reset(TMR_T* tmr);
552 void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig);
553 void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig);
554 void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig);
555 void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig);
556 void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig);
557 void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig);
558 void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig);
559 void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig);
560 void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig);
561 void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig);
562 void TMR_ConfigBDTStructInit(TMR_BDTConfig_T* BDTConfig);
563 void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode);
564 void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision);
565 void TMR_Enable(TMR_T* tmr);
566 void TMR_Disable(TMR_T* tmr);
567 
568 /* PWM Configuration */
569 void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig);
570 void TMR_EnablePWMOutputs(TMR_T* tmr);
571 void TMR_DisablePWMOutputs(TMR_T* tmr);
572 
573 /* DMA */
574 void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
575 void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource);
576 void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource);
577 
578 /* Configuration */
579 void TMR_ConfigInternalClock(TMR_T* tmr);
580 void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource);
581 void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
582                                  TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
583 void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
584                              TMR_EXTTRG_POL_T polarity, uint16_t filter);
585 void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
586                              TMR_EXTTRG_POL_T polarity, uint16_t filter);
587 void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
588                    TMR_EXTTRG_POL_T polarity, uint16_t filter);
589 void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode);
590 void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode);
591 void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
592 void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
593                                TMR_IC_POLARITY_T IC2Polarity);
594 void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction);
595 void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction);
596 void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction);
597 void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction);
598 void TMR_EnableAutoReload(TMR_T* tmr);
599 void TMR_DisableAutoReload(TMR_T* tmr);
600 void TMR_EnableSelectCOM(TMR_T* tmr);
601 void TMR_DisableSelectCOM(TMR_T* tmr);
602 void TMR_EnableCCDMA(TMR_T* tmr);
603 void TMR_DisableCCDMA(TMR_T* tmr);
604 void TMR_EnableCCPreload(TMR_T* tmr);
605 void TMR_DisableCCPreload(TMR_T* tmr);
606 void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
607 void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
608 void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
609 void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
610 void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
611 void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
612 void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
613 void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
614 void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
615 void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
616 void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
617 void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
618 void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
619 void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
620 void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
621 void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
622 void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
623 void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
624 void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
625 void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel);
626 void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel);
627 void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel);
628 void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel);
629 void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
630 void TMR_EnableUpdate(TMR_T* tmr);
631 void TMR_DisableUpdate(TMR_T* tmr);
632 void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource);
633 void TMR_EnableHallSensor(TMR_T* tmr);
634 void TMR_DisableHallSensor(TMR_T* tmr);
635 
636 void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource);
637 void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode);
638 void TMR_EnableMasterSlaveMode(TMR_T* tmr);
639 void TMR_DisableMasterSlaveMode(TMR_T* tmr);
640 void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter);
641 void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload);
642 void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1);
643 void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2);
644 void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3);
645 void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4);
646 void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
647 void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
648 void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
649 void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
650 
651 uint16_t TMR_ReadCaputer1(TMR_T* tmr);
652 uint16_t TMR_ReadCaputer2(TMR_T* tmr);
653 uint16_t TMR_ReadCaputer3(TMR_T* tmr);
654 uint16_t TMR_ReadCaputer4(TMR_T* tmr);
655 uint16_t TMR_ReadCounter(TMR_T* tmr);
656 uint16_t TMR_ReadPrescaler(TMR_T* tmr);
657 
658 /* Interrupts and Event */
659 void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt);
660 void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt);
661 void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources);
662 
663 /* flags */
664 uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag);
665 void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag);
666 uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag);
667 void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag);
668 
669 /**@} end of group TMR_Functions */
670 /**@} end of group TMR_Driver */
671 /**@} end of group APM32F10x_StdPeriphDriver */
672 
673 #ifdef __cplusplus
674 }
675 #endif
676 
677 #endif /* __APM32F10X_TMR_H */
678