1 /*! 2 * @file apm32f4xx_adc.h 3 * 4 * @brief This file contains all the functions prototypes for the ADC firmware library 5 * 6 * @version V1.0.2 7 * 8 * @date 2022-06-23 9 * 10 * @attention 11 * 12 * Copyright (C) 2021-2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be usefull and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32F4XX_ADC_H 28 #define __APM32F4XX_ADC_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* Includes */ 35 #include "apm32f4xx.h" 36 37 /** @addtogroup APM32F4xx_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup ADC_Driver 42 @{ 43 */ 44 45 /** @defgroup ADC_Enumerations 46 @{ 47 */ 48 49 /** 50 * @brief ADC Common mode 51 */ 52 typedef enum 53 { 54 /* All the ADCs independent */ 55 ADC_MODE_INDEPENDENT = (uint8_t)0x00, /*!< Independent mode */ 56 57 /* ADC1 and ADC2 working together but ADC3 is independent */ 58 ADC_MODE_DUAL_REGSIMULT_INJECSIMULT = (uint8_t)0x01, /*!< regular simultaneous + injected simultaneous */ 59 ADC_MODE_DUAL_REGSIMULT_ALTERTRIG = (uint8_t)0x02, /*!< regular simultaneous + alternate trigger */ 60 ADC_MODE_DUAL_INJECSIMULT = (uint8_t)0x05, /*!< Injected simultaneous mode only */ 61 ADC_MODE_DUAL_REGSIMULT = (uint8_t)0x06, /*!< Regular simultaneous mode only */ 62 ADC_MODE_DUAL_INTERL = (uint8_t)0x07, /*!< Interleaved mode only */ 63 ADC_MODE_DUAL_ALTERTRIG = (uint8_t)0x09, /*!< Alternate trigger mode only */ 64 65 /* ADC1, ADC2 and ADC3 working together */ 66 ADC_MODE_TRIPLE_REGSIMULT_INJECSIMULT = (uint8_t)0x11, /*!< regular simultaneous + injected simultaneous */ 67 ADC_MODE_TRIPLE_REGSIMULT_ALTERTRIG = (uint8_t)0x12, /*!< regular simultaneous + alternate trigger */ 68 ADC_MODE_TRIPLE_INJECSIMULT = (uint8_t)0x15, /*!< Injected simultaneous mode only */ 69 ADC_MODE_TRIPLE_REGSIMULT = (uint8_t)0x16, /*!< Regular simultaneous mode only */ 70 ADC_MODE_TRIPLE_INTERL = (uint8_t)0x17, /*!< Interleaved mode only */ 71 ADC_MODE_TRIPLE_ALTERTRIG = (uint8_t)0x19 /*!< Alternate trigger mode only */ 72 } ADC_MODE_T; 73 74 /** 75 * @brief ADC Prescaler 76 */ 77 typedef enum 78 { 79 ADC_PRESCALER_DIV2, /*!< PCLK2 2 divided frequency */ 80 ADC_PRESCALER_DIV4, /*!< PCLK2 4 divided frequency */ 81 ADC_PRESCALER_DIV6, /*!< PCLK2 6 divided frequency */ 82 ADC_PRESCALER_DIV8 /*!< PCLK2 8 divided frequency */ 83 } ADC_PRESCALER_T; 84 85 /** 86 * @brief ADC Direct memory access mode for multi mode 87 */ 88 typedef enum 89 { 90 ADC_ACCESS_MODE_DISABLED, /*!< DMA mode disabled */ 91 ADC_ACCESS_MODE_1, /*!< DMA mode 1 enabled (2/3 half-words one by one - 1 then 2 then 3) */ 92 ADC_ACCESS_MODE_2, /*!< DMA mode 2 enabled (2/3 half-words by pairs - 2&1 then 1&3 then 3&2) */ 93 ADC_ACCESS_MODE_3 /*!< DMA mode 3 enabled (2/3 bytes by pairs - 2&1 then 1&3 then 3&2) */ 94 } ADC_ACCESS_MODE_T; 95 96 /** 97 * @brief ADC Delay between 2 sampling phases 98 */ 99 typedef enum 100 { 101 ADC_TWO_SAMPLING_5CYCLES, /*!< 5*Tadcclk delay between 2 sampling phases */ 102 ADC_TWO_SAMPLING_6CYCLES, /*!< 6*Tadcclk delay between 2 sampling phases */ 103 ADC_TWO_SAMPLING_7CYCLES, /*!< 7*Tadcclk delay between 2 sampling phases */ 104 ADC_TWO_SAMPLING_8CYCLES, /*!< 8*Tadcclk delay between 2 sampling phases */ 105 ADC_TWO_SAMPLING_9CYCLES, /*!< 9*Tadcclk delay between 2 sampling phases */ 106 ADC_TWO_SAMPLING_10CYCLES, /*!< 10*Tadcclk delay between 2 sampling phases */ 107 ADC_TWO_SAMPLING_11CYCLES, /*!< 11*Tadcclk delay between 2 sampling phases */ 108 ADC_TWO_SAMPLING_12CYCLES, /*!< 12*Tadcclk delay between 2 sampling phases */ 109 ADC_TWO_SAMPLING_13CYCLES, /*!< 13*Tadcclk delay between 2 sampling phases */ 110 ADC_TWO_SAMPLING_14CYCLES, /*!< 14*Tadcclk delay between 2 sampling phases */ 111 ADC_TWO_SAMPLING_15CYCLES, /*!< 15*Tadcclk delay between 2 sampling phases */ 112 ADC_TWO_SAMPLING_16CYCLES, /*!< 16*Tadcclk delay between 2 sampling phases */ 113 ADC_TWO_SAMPLING_17CYCLES, /*!< 17*Tadcclk delay between 2 sampling phases */ 114 ADC_TWO_SAMPLING_18CYCLES, /*!< 18*Tadcclk delay between 2 sampling phases */ 115 ADC_TWO_SAMPLING_19CYCLES, /*!< 19*Tadcclk delay between 2 sampling phases */ 116 ADC_TWO_SAMPLING_20CYCLES /*!< 20*Tadcclk delay between 2 sampling phases */ 117 } ADC_TWO_SAMPLING_T; 118 119 /** 120 * @brief ADC_resolution 121 */ 122 typedef enum 123 { 124 ADC_RESOLUTION_12BIT, /*!< ADC Resolution is 12 bits */ 125 ADC_RESOLUTION_10BIT, /*!< ADC Resolution is 10 bits */ 126 ADC_RESOLUTION_8BIT, /*!< ADC Resolution is 8 bits */ 127 ADC_RESOLUTION_6BIT /*!< ADC Resolution is 6 bits */ 128 } ADC_RESOLUTION_T; 129 130 /** 131 * @brief ADC External trigger edge for regular channels conversion 132 */ 133 typedef enum 134 { 135 ADC_EXT_TRIG_EDGE_NONE, /*!<Trigger detection is disabled */ 136 ADC_EXT_TRIG_EDGE_RISING, /*!<Trigger detection on rising edge */ 137 ADC_EXT_TRIG_EDGE_FALLING, /*!<Trigger detection on falling edge */ 138 ADC_EXT_TRIG_EDGE_RISING_FALLING, /*!<Trigger detection on rising edge and falling edge */ 139 } ADC_EXT_TRIG_EDGE_T; 140 141 /** 142 * @brief ADC External event trigger select for regular group 143 */ 144 typedef enum 145 { 146 ADC_EXT_TRIG_CONV_TMR1_CC1, /*!<Timer1 capture compare1 selected */ 147 ADC_EXT_TRIG_CONV_TMR1_CC2, /*!<Timer1 capture compare2 selected */ 148 ADC_EXT_TRIG_CONV_TMR1_CC3, /*!<Timer1 capture compare3 selected */ 149 ADC_EXT_TRIG_CONV_TMR2_CC2, /*!<Timer2 capture compare2 selected */ 150 ADC_EXT_TRIG_CONV_TMR2_CC3, /*!<Timer2 capture compare3 selected */ 151 ADC_EXT_TRIG_CONV_TMR2_CC4, /*!<Timer2 capture compare4 selected */ 152 ADC_EXT_TRIG_CONV_TMR2_TRGO, /*!<Timer2 TRGO event selected */ 153 ADC_EXT_TRIG_CONV_TMR3_CC1, /*!<Timer3 capture compare1 selected */ 154 ADC_EXT_TRIG_CONV_TMR3_TRGO, /*!<Timer3 TRGO event selected */ 155 ADC_EXT_TRIG_CONV_TMR4_CC4, /*!<Timer4 capture compare4 selected */ 156 ADC_EXT_TRIG_CONV_TMR5_CC1, /*!<Timer5 capture compare1 selected */ 157 ADC_EXT_TRIG_CONV_TMR5_CC2, /*!<Timer5 capture compare2 selected */ 158 ADC_EXT_TRIG_CONV_TMR5_CC3, /*!<Timer5 capture compare3 selected */ 159 ADC_EXT_TRIG_CONV_TMR8_CC1, /*!<Timer8 capture compare1 selected */ 160 ADC_EXT_TRIG_CONV_TMR8_TRGO, /*!<Timer8 TRGO event selected */ 161 ADC_EXT_TRIG_CONV_EINT_11 /*!<External interrupt line 11 event selected */ 162 } ADC_EXT_TRIG_CONV_T; 163 164 /** 165 * @brief ADC Data align 166 */ 167 typedef enum 168 { 169 ADC_DATA_ALIGN_RIGHT, /*!<Right alignment */ 170 ADC_DATA_ALIGN_LEFT /*!<Left alignment */ 171 } ADC_DATA_ALIGN_T; 172 173 /** 174 * @brief ADC Channel number 175 */ 176 typedef enum 177 { 178 ADC_CHANNEL_0, /*!< ADC Channel 0 */ 179 ADC_CHANNEL_1, /*!< ADC Channel 1 */ 180 ADC_CHANNEL_2, /*!< ADC Channel 2 */ 181 ADC_CHANNEL_3, /*!< ADC Channel 3 */ 182 ADC_CHANNEL_4, /*!< ADC Channel 4 */ 183 ADC_CHANNEL_5, /*!< ADC Channel 5 */ 184 ADC_CHANNEL_6, /*!< ADC Channel 6 */ 185 ADC_CHANNEL_7, /*!< ADC Channel 7 */ 186 ADC_CHANNEL_8, /*!< ADC Channel 8 */ 187 ADC_CHANNEL_9, /*!< ADC Channel 9 */ 188 ADC_CHANNEL_10, /*!< ADC Channel 10 */ 189 ADC_CHANNEL_11, /*!< ADC Channel 11 */ 190 ADC_CHANNEL_12, /*!< ADC Channel 12 */ 191 ADC_CHANNEL_13, /*!< ADC Channel 13 */ 192 ADC_CHANNEL_14, /*!< ADC Channel 14 */ 193 ADC_CHANNEL_15, /*!< ADC Channel 15 */ 194 ADC_CHANNEL_16, /*!< ADC Channel 16 */ 195 ADC_CHANNEL_17, /*!< ADC Channel 17 */ 196 ADC_CHANNEL_18, /*!< ADC Channel 18 */ 197 } ADC_CHANNEL_T; 198 199 /** 200 * @brief ADC_sampling_times 201 */ 202 typedef enum 203 { 204 ADC_SAMPLETIME_3CYCLES, /*!< Config the channel as 3 sample cyscles */ 205 ADC_SAMPLETIME_15CYCLES, /*!< Config the channel as 15 sample cyscles */ 206 ADC_SAMPLETIME_28CYCLES, /*!< Config the channel as 28 sample cyscles */ 207 ADC_SAMPLETIME_56CYCLES, /*!< Config the channel as 56 sample cyscles */ 208 ADC_SAMPLETIME_84CYCLES, /*!< Config the channel as 84 sample cyscles */ 209 ADC_SAMPLETIME_112CYCLES, /*!< Config the channel as 112 sample cyscles */ 210 ADC_SAMPLETIME_144CYCLES, /*!< Config the channel as 144 sample cyscles */ 211 ADC_SAMPLETIME_480CYCLES /*!< Config the channel as 480 sample cyscles */ 212 } ADC_SAMPLETIME_T; 213 214 /** 215 * @brief ADC external trigger edge for injected channels conversion 216 */ 217 typedef enum 218 { 219 ADC_EXT_TRIG_INJEC_EDGE_NONE, /*!< Disable the external trigger for injected channels */ 220 ADC_EXT_TRIG_INJEC_EDGE_RISING, /*!< Trigger detection on rising edge */ 221 ADC_EXT_TRIG_INJEC_EDGE_FALLING, /*!< Trigger detection on rising edge */ 222 ADC_EXT_TRIG_INJEC_EDGE_RISING_FALLING /*!< Trigger detection on rising edge and falling edge */ 223 } ADC_EXT_TRIG_INJEC_EDGE_T; 224 225 /** 226 * @brief ADC extrenal trigger sources for injected channels conversion 227 */ 228 typedef enum 229 { 230 ADC_EXT_TRIG_INJEC_CONV_TMR1_CC4, /*!< Timer1 capture compare 4 selected */ 231 ADC_EXT_TRIG_INJEC_CONV_TMR1_TRGO, /*!< Timer1 TRGO event selected */ 232 ADC_EXT_TRIG_INJEC_CONV_TMR2_CC1, /*!< Timer2 capture compare 1 selected */ 233 ADC_EXT_TRIG_INJEC_CONV_TMR2_TRGO, /*!< Timer2 TRGO event selected */ 234 ADC_EXT_TRIG_INJEC_CONV_TMR3_CC2, /*!< Timer3 capture compare 2 selected */ 235 ADC_EXT_TRIG_INJEC_CONV_TMR3_CC4, /*!< Timer3 capture compare 4 selected */ 236 ADC_EXT_TRIG_INJEC_CONV_TMR4_CC1, /*!< Timer4 capture compare 1 selected */ 237 ADC_EXT_TRIG_INJEC_CONV_TMR4_CC2, /*!< Timer4 capture compare 2 selected */ 238 ADC_EXT_TRIG_INJEC_CONV_TMR4_CC3, /*!< Timer4 capture compare 3 selected */ 239 ADC_EXT_TRIG_INJEC_CONV_TMR4_TRGO, /*!< Timer4 TRGO event selected */ 240 ADC_EXT_TRIG_INJEC_CONV_TMR5_CC4, /*!< Timer5 capture compare 4 selected */ 241 ADC_EXT_TRIG_INJEC_CONV_TMR5_TRGO, /*!< Timer5 TRGO event selected */ 242 ADC_EXT_TRIG_INJEC_CONV_TMR8_CC2, /*!< Timer8 capture compare 2 selected */ 243 ADC_EXT_TRIG_INJEC_CONV_TMR8_CC3, /*!< Timer8 capture compare 3 selected */ 244 ADC_EXT_TRIG_INJEC_CONV_TMR8_CC4, /*!< Timer8 capture compare 4 selected */ 245 ADC_EXT_TRIG_INJEC_CONV_EINT15 /*!< External interrupt line 15 event selected */ 246 } ADC_EXT_TRIG_INJEC_CONV_T; 247 248 /** 249 * @brief ADC injected channel selection 250 */ 251 typedef enum 252 { 253 ADC_INJEC_CHANNEL_1 = (uint8_t)0x01, /*!< Channel injected conversion Data */ 254 ADC_INJEC_CHANNEL_2 = (uint8_t)0x02, /*!< Channe2 injected conversion Data */ 255 ADC_INJEC_CHANNEL_3 = (uint8_t)0x03, /*!< Channe3 injected conversion Data */ 256 ADC_INJEC_CHANNEL_4 = (uint8_t)0x04 /*!< Channe4 injected conversion Data */ 257 } ADC_INJEC_CHANNEL_T; 258 259 /** 260 * @brief ADC analog watchdog selection 261 */ 262 typedef enum 263 { 264 ADC_ANALOG_WATCHDOG_SINGLE_INJEC = (uint8_t)0x11, /*!< Analog watchdog on a single injected channel */ 265 ADC_ANALOG_WATCHDOG_SINGLE_REG = (uint8_t)0x12, /*!< Analog watchdog on a single regular channel */ 266 ADC_ANALOG_WATCHDOG_SINGLE_REG_INJEC = (uint8_t)0x13, /*!< Analog watchdog on a single regular or injected channel */ 267 ADC_ANALOG_WATCHDOG_ALL_INJEC = (uint8_t)0x01, /*!< Analog watchdog on all injected channel */ 268 ADC_ANALOG_WATCHDOG_ALL_REG = (uint8_t)0x02, /*!< Analog watchdog on all regular channel */ 269 ADC_ANALOG_WATCHDOG_ALL_REG_ALL_INJEC = (uint8_t)0x03, /*!< Analog watchdog on all regular and injected channels */ 270 ADC_ANALOG_WATCHDOG_NONE = (uint8_t)0x00 /*!< No Analog watchdog */ 271 } ADC_ANALOG_WATCHDOG_T; 272 273 /** 274 * @brief ADC interrupts 275 */ 276 typedef enum 277 { 278 ADC_INT_EOC = BIT5, /*!< End of conversion interrupt mask */ 279 ADC_INT_AWD = BIT6, /*!< Analog watchdog interrupt mask */ 280 ADC_INT_INJEOC = BIT7, /*!< End of injected conversion interrupt mask */ 281 ADC_INT_OVR = BIT26 /*!< Overrun interrupt enable */ 282 } ADC_INT_T; 283 284 /** 285 * @brief ADC interrupt flags 286 */ 287 typedef enum 288 { 289 ADC_INT_FLAG_AWD = 0x0501, /*!< Analog watchdog interrupt flag */ 290 ADC_INT_FLAG_EOC = 0x0602, /*!< End of conversion interrupt flag */ 291 ADC_INT_FLAG_INJEOC = 0x0704, /*!< End of injected conversion interrupt flag */ 292 ADC_INT_FLAG_OVR = 0x1A20 /*!< Overrun interrupt flag */ 293 } ADC_INT_FLAG_T; 294 295 /** 296 * @brief ADC status flags 297 */ 298 typedef enum 299 { 300 ADC_FLAG_AWD = BIT0, /*!< Analog watchdog flag */ 301 ADC_FLAG_EOC = BIT1, /*!< End of conversion flag */ 302 ADC_FLAG_INJEOC = BIT2, /*!< End of injected group conversion flag */ 303 ADC_FLAG_INJCS = BIT3, /*!< Start of injected group conversion flag */ 304 ADC_FLAG_REGCS = BIT4, /*!< Start of regular group conversion flag */ 305 ADC_FLAG_OVR = BIT5 /*!< Overrun flag */ 306 } ADC_FLAG_T; 307 308 /**@} end of group ADC_Enumerations*/ 309 310 /** @defgroup ADC_Structure 311 @{ 312 */ 313 314 /** 315 * @brief ADC configuration Mode 316 */ 317 typedef struct 318 { 319 ADC_RESOLUTION_T resolution; /*!< Configures the ADC resolution dual mode. 320 This parameter can be a value of @ref ADC_RESOLUTION_T */ 321 uint8_t scanConvMode; /*!< This value can be ENABLE or DISABLE */ 322 uint8_t continuousConvMode; /*!< This value can be ENABLE or DISABLE */ 323 ADC_EXT_TRIG_EDGE_T extTrigEdge; /*!< Enable the External Trigger for Regular Channels */ 324 ADC_EXT_TRIG_CONV_T extTrigConv; /*!< Select the External Trigger Event to Start the 325 Regular Group Conversion */ 326 ADC_DATA_ALIGN_T dataAlign; /*!< Data Alignment Mode Configure */ 327 uint8_t nbrOfChannel; /*!< regular channel sequence length can be from 1 to 16 */ 328 } ADC_Config_T; 329 330 /** 331 * @brief ADC Common Init structure definition 332 */ 333 typedef struct 334 { 335 ADC_MODE_T mode; /*!< ADC mode selection */ 336 ADC_PRESCALER_T prescaler; /*!< ADC Prescaler */ 337 ADC_ACCESS_MODE_T accessMode; /*!< DMA Mode */ 338 ADC_TWO_SAMPLING_T twoSampling; /*!< Delay Between 2 Sampling Phases */ 339 } ADC_CommonConfig_T; 340 341 /**@} end of group ADC_Structure*/ 342 343 /** @defgroup ADC_Functions 344 @{ 345 */ 346 347 /* ADC Reset */ 348 void ADC_Reset(void); 349 350 /* Configuration */ 351 void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig); 352 void ADC_ConfigStructInit(ADC_Config_T* adcConfig); 353 void ADC_CommonConfig(ADC_CommonConfig_T* adcCommonConfig); 354 void ADC_CommonConfigStructInit(ADC_CommonConfig_T* adcCommonConfig); 355 void ADC_Enable(ADC_T* adc); 356 void ADC_Disable(ADC_T* adc); 357 358 /* Analog Watchdog */ 359 void ADC_EnableAnalogWatchdog(ADC_T* adc, ADC_ANALOG_WATCHDOG_T analogWatchdog); 360 void ADC_DisableAnalogWatchdog(ADC_T* adc); 361 void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold); 362 void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel); 363 364 /* Temperature Sensor, Vrefint and VBAT management **/ 365 void ADC_EnableTempSensorVrefint(void); 366 void ADC_DisableTempSensorVrefint(void); 367 void ADC_EnableVbat(void); 368 void ADC_DisableVbat(void); 369 370 /* Regular Channels Configuration */ 371 void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel, 372 uint8_t rank, uint8_t sampleTime); 373 void ADC_SoftwareStartConv(ADC_T* adc); 374 uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc); 375 376 void ADC_EnableEOCOnEachChannel(ADC_T* adc); 377 void ADC_DisableEOCOnEachChannel(ADC_T* adc); 378 379 /* Continuous Mode */ 380 void ADC_EnableContinuousMode(ADC_T* adc); 381 void ADC_DisableContinuousMode(ADC_T* adc); 382 383 /* Discontinuous Mode */ 384 void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number); 385 void ADC_EnableDiscMode(ADC_T* adc); 386 void ADC_DisableDiscMode(ADC_T* adc); 387 388 uint16_t ADC_ReadConversionValue(ADC_T* adc); 389 uint32_t ADC_ReadMultiValue(void); 390 391 /* Regular Channels DMA */ 392 void ADC_EnableDMA(ADC_T* adc); 393 void ADC_DisableDMA(ADC_T* adc); 394 395 void ADC_EnableDMARequest(ADC_T* adc); 396 void ADC_DisableDMARequest(ADC_T* adc); 397 398 void ADC_EnableMultiModeDMARequest(void); 399 void ADC_DisableMultiModeDMARequest(void); 400 401 /* Injected channels Configuration functions */ 402 void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, 403 uint8_t sampleTime); 404 void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length); 405 void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offset); 406 void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv); 407 void ADC_ConfigExternalTrigInjectedConvEdge(ADC_T* adc, ADC_EXT_TRIG_INJEC_EDGE_T extTrigInjecConvEdge); 408 void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc); 409 uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc); 410 void ADC_EnableAutoInjectedConv(ADC_T* adc); 411 void ADC_DisableAutoInjectedConv(ADC_T* adc); 412 void ADC_EnableInjectedDiscMode(ADC_T* adc); 413 void ADC_DisableInjectedDiscMode(ADC_T* adc); 414 uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel); 415 416 /* Interrupts and flags */ 417 void ADC_EnableInterrupt(ADC_T* adc, uint32_t interrupt); 418 void ADC_DisableInterrupt(ADC_T* adc, uint32_t interrupt); 419 uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag); 420 void ADC_ClearStatusFlag(ADC_T* adc, uint32_t flag); 421 uint16_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_FLAG_T flag); 422 void ADC_ClearIntFlag(ADC_T* adc, uint32_t flag); 423 424 #ifdef __cplusplus 425 } 426 #endif 427 428 #endif /* __APM32F4XX_ADC_H */ 429 430 /**@} end of group ADC_Functions */ 431 /**@} end of group ADC_Driver */ 432 /**@} end of group APM32F4xx_StdPeriphDriver */ 433