1 /*! 2 * @file apm32f4xx_rcm.h 3 * 4 * @brief This file contains all the functions prototypes for the RCM firmware library 5 * 6 * @version V1.0.2 7 * 8 * @date 2022-06-23 9 * 10 * @attention 11 * 12 * Copyright (C) 2021-2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be usefull and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32F4XX_RCM_H 28 #define __APM32F4XX_RCM_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* Includes */ 35 #include "apm32f4xx.h" 36 37 /** @addtogroup APM32F4xx_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup RCM_Driver 42 @{ 43 */ 44 45 /** @defgroup RCM_Enumerations 46 @{ 47 */ 48 49 /** 50 * @brief HSE state 51 */ 52 typedef enum 53 { 54 RCM_HSE_CLOSE, /*!< Turn off the HSE oscillator */ 55 RCM_HSE_OPEN, /*!< Turn on the HSE oscillator */ 56 RCM_HSE_BYPASS /*!< HSE oscillator bypassed with external clock */ 57 } RCM_HSE_T; 58 59 /** 60 * @brief LSE State 61 */ 62 typedef enum 63 { 64 RCM_LSE_CLOSE, /*!< Close the LSE */ 65 RCM_LSE_OPEN, /*!< Open the LSE */ 66 RCM_LSE_BYPASS /*!< LSE bypass */ 67 } RCM_LSE_T; 68 69 /** 70 * @brief RCM PLL source select 71 */ 72 typedef enum 73 { 74 RCM_PLLSEL_HSI, /*!< HSI oscillator clock selected as PLL clock entry */ 75 RCM_PLLSEL_HSE /*!< HSE oscillator clock selected as PLL clock entry */ 76 } RCM_PLLSEL_T; 77 78 /** 79 * @brief RCM PLL System Division 80 */ 81 typedef enum 82 { 83 RCM_PLL_SYS_DIV_2, /*!< System clock Division factor is 2 */ 84 RCM_PLL_SYS_DIV_4, /*!< System clock Division factor is 4 */ 85 RCM_PLL_SYS_DIV_6, /*!< System clock Division factor is 6 */ 86 RCM_PLL_SYS_DIV_8 /*!< System clock Division factor is 8 */ 87 } RCM_PLL_SYS_DIV_T; 88 89 /** 90 * @brief RCM MCO1 Source Selece 91 */ 92 typedef enum 93 { 94 RCM_MCO1_SEL_HSICLK, /*!< HSI clock selected as MCO1 source */ 95 RCM_MCO1_SEL_LSECLK, /*!< LSE clock selected as MCO1 source */ 96 RCM_MCO1_SEL_HSECLK, /*!< HSE clock selected as MCO1 source */ 97 RCM_MCO1_SEL_PLLCLK /*!< Main PLL clock selected as MCO1 source */ 98 } RCM_MCO1_SEL_T; 99 100 /** 101 * @brief RCM MCO1 Div 102 */ 103 typedef enum 104 { 105 RCM_MCO1_DIV_1, /*!< No division applied to MCO1 clock */ 106 RCM_MCO1_DIV_2 = 4, /*!< Division by 2 applied to MCO1 clock */ 107 RCM_MCO1_DIV_3, /*!< Division by 3 applied to MCO1 clock */ 108 RCM_MCO1_DIV_4, /*!< Division by 4 applied to MCO1 clock */ 109 RCM_MCO1_DIV_5 /*!< Division by 5 applied to MCO1 clock */ 110 } RCM_MCO1_DIV_T; 111 112 /** 113 * @brief RCM MCO2 Source Selece 114 */ 115 typedef enum 116 { 117 RCM_MCO2_SEL_SYSCLK, /*!< SYS clock selected as MCO2 source */ 118 RCM_MCO2_SEL_PLL2CLK, /*!< PLL2 clock selected as MCO2 source */ 119 RCM_MCO2_SEL_HSECLK, /*!< HSE clock selected as MCO2 source */ 120 RCM_MCO2_SEL_PLLCLK /*!< PLL clock selected as MCO2 source */ 121 } RCM_MCO2_SEL_T; 122 123 /** 124 * @brief RCM MCO2 Division 125 */ 126 typedef enum 127 { 128 RCM_MCO2_DIV_1, /*!< No division applied to MCO2 clock */ 129 RCM_MCO2_DIV_2 = 4, /*!< Division by 2 applied to MCO2 clock */ 130 RCM_MCO2_DIV_3, /*!< Division by 3 applied to MCO2 clock */ 131 RCM_MCO2_DIV_4, /*!< Division by 4 applied to MCO2 clock */ 132 RCM_MCO2_DIV_5 /*!< Division by 5 applied to MCO2 clock */ 133 } RCM_MCO2_DIV_T; 134 135 /** 136 * @brief System clock select 137 */ 138 typedef enum 139 { 140 RCM_SYSCLK_SEL_HSI, /*!< HSI is selected as system clock source */ 141 RCM_SYSCLK_SEL_HSE, /*!< HSE is selected as system clock source */ 142 RCM_SYSCLK_SEL_PLL /*!< PLL is selected as system clock source */ 143 } RCM_SYSCLK_SEL_T; 144 145 /** 146 * @brief AHB divider Number 147 */ 148 typedef enum 149 { 150 RCM_AHB_DIV_1 = 7, /*!< HCLK = SYSCLK */ 151 RCM_AHB_DIV_2, /*!< HCLK = SYSCLK / 2 */ 152 RCM_AHB_DIV_4, /*!< HCLK = SYSCLK / 4 */ 153 RCM_AHB_DIV_8, /*!< HCLK = SYSCLK / 8 */ 154 RCM_AHB_DIV_16, /*!< HCLK = SYSCLK / 16 */ 155 RCM_AHB_DIV_64, /*!< HCLK = SYSCLK / 64 */ 156 RCM_AHB_DIV_128, /*!< HCLK = SYSCLK / 128 */ 157 RCM_AHB_DIV_256, /*!< HCLK = SYSCLK / 256 */ 158 RCM_AHB_DIV_512 /*!< HCLK = SYSCLK / 512 */ 159 } RCM_AHB_DIV_T; 160 161 /** 162 * @brief APB divider Number 163 */ 164 typedef enum 165 { 166 RCM_APB_DIV_1 = 3, /*!< PCLK1 = HCLK */ 167 RCM_APB_DIV_2, /*!< PCLK1 = HCLK / 2 */ 168 RCM_APB_DIV_4, /*!< PCLK1 = HCLK / 4 */ 169 RCM_APB_DIV_8, /*!< PCLK1 = HCLK / 8 */ 170 RCM_APB_DIV_16 /*!< PCLK1 = HCLK / 16 */ 171 } RCM_APB_DIV_T; 172 173 /** 174 * @brief SDRAM divider Number 175 */ 176 typedef enum 177 { 178 RCM_SDRAM_DIV_1 = 0, /*!< SDRAM clock = DMC clock */ 179 RCM_SDRAM_DIV_2 = 1, /*!< SDRAM clock = DMC clock / 2 */ 180 RCM_SDRAM_DIV_4 = 2, /*!< SDRAM clock = DMC clock / 4 */ 181 } RCM_SDRAM_DIV_T; 182 183 /** 184 * @brief RTC clock select 185 */ 186 typedef enum 187 { 188 RCM_RTCCLK_LSE, /*!< RTCCLK = LSE clock */ 189 RCM_RTCCLK_LSI, /*!< RTCCLK = LSI clock */ 190 RCM_RTCCLK_HSE_DIV2, /*!< RTCCLK = HSE / 2 */ 191 RCM_RTCCLK_HSE_DIV3, /*!< RTCCLK = HSE / 3 */ 192 RCM_RTCCLK_HSE_DIV4, /*!< RTCCLK = HSE / 4 */ 193 RCM_RTCCLK_HSE_DIV5, /*!< RTCCLK = HSE / 5 */ 194 RCM_RTCCLK_HSE_DIV6, /*!< RTCCLK = HSE / 6 */ 195 RCM_RTCCLK_HSE_DIV7, /*!< RTCCLK = HSE / 7 */ 196 RCM_RTCCLK_HSE_DIV8, /*!< RTCCLK = HSE / 8 */ 197 RCM_RTCCLK_HSE_DIV9, /*!< RTCCLK = HSE / 9 */ 198 RCM_RTCCLK_HSE_DIV10, /*!< RTCCLK = HSE / 10 */ 199 RCM_RTCCLK_HSE_DIV11, /*!< RTCCLK = HSE / 11 */ 200 RCM_RTCCLK_HSE_DIV12, /*!< RTCCLK = HSE / 12 */ 201 RCM_RTCCLK_HSE_DIV13, /*!< RTCCLK = HSE / 13 */ 202 RCM_RTCCLK_HSE_DIV14, /*!< RTCCLK = HSE / 14 */ 203 RCM_RTCCLK_HSE_DIV15, /*!< RTCCLK = HSE / 15 */ 204 RCM_RTCCLK_HSE_DIV16, /*!< RTCCLK = HSE / 16 */ 205 RCM_RTCCLK_HSE_DIV17, /*!< RTCCLK = HSE / 17 */ 206 RCM_RTCCLK_HSE_DIV18, /*!< RTCCLK = HSE / 18 */ 207 RCM_RTCCLK_HSE_DIV19, /*!< RTCCLK = HSE / 19 */ 208 RCM_RTCCLK_HSE_DIV20, /*!< RTCCLK = HSE / 20 */ 209 RCM_RTCCLK_HSE_DIV21, /*!< RTCCLK = HSE / 21 */ 210 RCM_RTCCLK_HSE_DIV22, /*!< RTCCLK = HSE / 22 */ 211 RCM_RTCCLK_HSE_DIV23, /*!< RTCCLK = HSE / 23 */ 212 RCM_RTCCLK_HSE_DIV24, /*!< RTCCLK = HSE / 24 */ 213 RCM_RTCCLK_HSE_DIV25, /*!< RTCCLK = HSE / 25 */ 214 RCM_RTCCLK_HSE_DIV26, /*!< RTCCLK = HSE / 26 */ 215 RCM_RTCCLK_HSE_DIV27, /*!< RTCCLK = HSE / 27 */ 216 RCM_RTCCLK_HSE_DIV28, /*!< RTCCLK = HSE / 28 */ 217 RCM_RTCCLK_HSE_DIV29, /*!< RTCCLK = HSE / 29 */ 218 RCM_RTCCLK_HSE_DIV30, /*!< RTCCLK = HSE / 30 */ 219 RCM_RTCCLK_HSE_DIV31 /*!< RTCCLK = HSE / 31 */ 220 } RCM_RTCCLK_T; 221 222 /** 223 * @brief I2S Clock Source 224 */ 225 typedef enum 226 { 227 RCM_I2S_CLK_PLLI2S, /*!< PLLI2S is selected as I2S clock source */ 228 RCM_I2S_CLK_EXT /*!< EXT is selected as I2S clock source */ 229 } RCM_I2S_CLK_T; 230 231 /** 232 * @brief RCM Interrupt Source 233 */ 234 typedef enum 235 { 236 RCM_INT_LSIRDY = BIT0, /*!< LSI ready interrupt */ 237 RCM_INT_LSERDY = BIT1, /*!< LSE ready interrupt */ 238 RCM_INT_HSIRDY = BIT2, /*!< HSI ready interrupt */ 239 RCM_INT_HSERDY = BIT3, /*!< HSE ready interrupt */ 240 RCM_INT_PLL1RDY = BIT4, /*!< PLL1 ready interrupt */ 241 RCM_INT_PLL2RDY = BIT5, /*!< PLL2 ready interrupt */ 242 RCM_INT_CSS = BIT7 /*!< Clock security system interrupt */ 243 } RCM_INT_T; 244 245 /** 246 * @brief AHB1 peripheral 247 */ 248 typedef enum 249 { 250 RCM_AHB1_PERIPH_GPIOA = BIT0, /*!< Select GPIOA clock */ 251 RCM_AHB1_PERIPH_GPIOB = BIT1, /*!< Select GPIOB clock */ 252 RCM_AHB1_PERIPH_GPIOC = BIT2, /*!< Select GPIOC clock */ 253 RCM_AHB1_PERIPH_GPIOD = BIT3, /*!< Select GPIOD clock */ 254 RCM_AHB1_PERIPH_GPIOE = BIT4, /*!< Select GPIOE clock */ 255 RCM_AHB1_PERIPH_GPIOF = BIT5, /*!< Select GPIOF clock */ 256 RCM_AHB1_PERIPH_GPIOG = BIT6, /*!< Select GPIOG clock */ 257 RCM_AHB1_PERIPH_GPIOH = BIT7, /*!< Select GPIOH clock */ 258 RCM_AHB1_PERIPH_GPIOI = BIT8, /*!< Select GPIOI clock */ 259 RCM_AHB1_PERIPH_GPIOJ = BIT9, /*!< Select GPIOJ clock */ 260 RCM_AHB1_PERIPH_GPIOK = BIT10, /*!< Select GPIOK clock */ 261 RCM_AHB1_PERIPH_CRC = BIT12, /*!< Select CRC clock */ 262 RCM_AHB1_PERIPH_FLITF = BIT15, /*!< Select FLITF clock */ 263 RCM_AHB1_PERIPH_SRAM1 = BIT16, /*!< Select SRAM1 clock */ 264 RCM_AHB1_PERIPH_SRAM2 = BIT17, /*!< Select SRAM2 clock */ 265 RCM_AHB1_PERIPH_BKPSRAM = BIT18, /*!< Select BKPSRAM clock */ 266 RCM_AHB1_PERIPH_SRAM3 = BIT19, /*!< Select SRAM3 clock */ 267 RCM_AHB1_PERIPH_CCMDATARAMEN = BIT20, /*!< Select CCMDATARAMEN clock */ 268 RCM_AHB1_PERIPH_DMA1 = BIT21, /*!< Select DMA1 clock */ 269 RCM_AHB1_PERIPH_DMA2 = BIT22, /*!< Select DMA2 clock */ 270 RCM_AHB1_PERIPH_ETH_MAC = BIT25, /*!< Select ETH MAC clock */ 271 RCM_AHB1_PERIPH_ETH_MAC_Tx = BIT26, /*!< Select ETH MAC TX clock */ 272 RCM_AHB1_PERIPH_ETH_MAC_Rx = BIT27, /*!< Select ETH MAC RX clock */ 273 RCM_AHB1_PERIPH_ETH_MAC_PTP = BIT28, /*!< Select ETH MAC PTP clock */ 274 RCM_AHB1_PERIPH_OTG_HS = BIT29, /*!< Select OTG HS clock */ 275 RCM_AHB1_PERIPH_OTG_HS_ULPI = BIT30 /*!< Select OTG HS ULPI clock */ 276 } RCM_AHB1_PERIPH_T; 277 278 /** 279 * @brief AHB2 peripheral 280 */ 281 typedef enum 282 { 283 RCM_AHB2_PERIPH_DCI = BIT0, /*!< Select DCI clock */ 284 RCM_AHB2_PERIPH_FPU = BIT1, /*!< Select FPU clock */ 285 RCM_AHB2_PERIPH_BN = BIT2, /*!< Select BN clock */ 286 RCM_AHB2_PERIPH_SM = BIT3, /*!< Select SM clock */ 287 RCM_AHB2_PERIPH_CRYP = BIT4, /*!< Select CRYP clock */ 288 RCM_AHB2_PERIPH_HASH = BIT5, /*!< Select HASH clock */ 289 RCM_AHB2_PERIPH_RNG = BIT6, /*!< Select RNG clock */ 290 RCM_AHB2_PERIPH_OTG_FS = BIT7 /*!< Select OTG FS clock */ 291 } RCM_AHB2_PERIPH_T; 292 293 /** 294 * @brief APB1 peripheral 295 */ 296 typedef enum 297 { 298 RCM_APB1_PERIPH_TMR2 = BIT0, /*!< Select TMR2 clock */ 299 RCM_APB1_PERIPH_TMR3 = BIT1, /*!< Select TMR3 clock */ 300 RCM_APB1_PERIPH_TMR4 = BIT2, /*!< Select TMR4 clock */ 301 RCM_APB1_PERIPH_TMR5 = BIT3, /*!< Select TMR5 clock */ 302 RCM_APB1_PERIPH_TMR6 = BIT4, /*!< Select TMR6 clock */ 303 RCM_APB1_PERIPH_TMR7 = BIT5, /*!< Select TMR7 clock */ 304 RCM_APB1_PERIPH_TMR12 = BIT6, /*!< Select TMR12 clock */ 305 RCM_APB1_PERIPH_TMR13 = BIT7, /*!< Select TMR13 clock */ 306 RCM_APB1_PERIPH_TMR14 = BIT8, /*!< Select TMR14 clock */ 307 RCM_APB1_PERIPH_WWDT = BIT11, /*!< Select WWDT clock */ 308 RCM_APB1_PERIPH_SPI2 = BIT14, /*!< Select SPI2 clock */ 309 RCM_APB1_PERIPH_SPI3 = BIT15, /*!< Select SPI3 clock */ 310 RCM_APB1_PERIPH_USART2 = BIT17, /*!< Select USART2 clock */ 311 RCM_APB1_PERIPH_USART3 = BIT18, /*!< Select USART3 clock */ 312 RCM_APB1_PERIPH_UART4 = BIT19, /*!< Select UART4 clock */ 313 RCM_APB1_PERIPH_UART5 = BIT20, /*!< Select UART5 clock */ 314 RCM_APB1_PERIPH_I2C1 = BIT21, /*!< Select I2C1 clock */ 315 RCM_APB1_PERIPH_I2C2 = BIT22, /*!< Select I2C2 clock */ 316 RCM_APB1_PERIPH_I2C3 = BIT23, /*!< Select I2C3 clock */ 317 RCM_APB1_PERIPH_CAN1 = BIT25, /*!< Select CAN1 clock */ 318 RCM_APB1_PERIPH_CAN2 = BIT26, /*!< Select CAN2 clock */ 319 RCM_APB1_PERIPH_PMU = BIT28, /*!< Select PMU clock */ 320 RCM_APB1_PERIPH_DAC = BIT29, /*!< Select DAC clock */ 321 RCM_APB1_PERIPH_UART7 = BIT30, /*!< Select UART7 clock */ 322 RCM_APB1_PERIPH_UART8 = (int32_t)BIT31 /*!< Select UART8 clock */ 323 } RCM_APB1_PERIPH_T; 324 325 /** 326 * @brief APB2 peripheral 327 */ 328 typedef enum 329 { 330 RCM_APB2_PERIPH_TMR1 = BIT0, /*!< Select TMR1 clock */ 331 RCM_APB2_PERIPH_TMR8 = BIT1, /*!< Select TMR8 clock */ 332 RCM_APB2_PERIPH_USART1 = BIT4, /*!< Select USART1 clock */ 333 RCM_APB2_PERIPH_USART6 = BIT5, /*!< Select USART6 clock */ 334 RCM_APB2_PERIPH_ADC = BIT8, /*!< Select ADC clock */ 335 RCM_APB2_PERIPH_ADC1 = BIT8, /*!< Select ADC1 clock */ 336 RCM_APB2_PERIPH_ADC2 = BIT9, /*!< Select ADC2 clock */ 337 RCM_APB2_PERIPH_ADC3 = BIT10, /*!< Select ADC3 clock */ 338 RCM_APB2_PERIPH_SDIO = BIT11, /*!< Select SDIO clock */ 339 RCM_APB2_PERIPH_SPI1 = BIT12, /*!< Select SPI1 clock */ 340 RCM_APB2_PERIPH_SPI4 = BIT13, /*!< Select SPI4 clock */ 341 RCM_APB2_PERIPH_SYSCFG = BIT14, /*!< Select SYSCFG clock */ 342 RCM_APB2_PERIPH_EXTIT = BIT15, /*!< Select EXTIT clock */ 343 RCM_APB2_PERIPH_TMR9 = BIT16, /*!< Select TMR9 clock */ 344 RCM_APB2_PERIPH_TMR10 = BIT17, /*!< Select TMR10 clock */ 345 RCM_APB2_PERIPH_TMR11 = BIT18, /*!< Select TMR11 clock */ 346 RCM_APB2_PERIPH_SPI5 = BIT20, /*!< Select SPI5 clock */ 347 RCM_APB2_PERIPH_SPI6 = BIT21, /*!< Select SPI6 clock */ 348 RCM_APB2_PERIPH_SAI1 = BIT22, /*!< Select SAI1 clock */ 349 RCM_APB2_PERIPH_LTDC = BIT26 /*!< Select LTDC clock */ 350 } RCM_APB2_PERIPH_T; 351 352 /** 353 * @brief RCM FLAG define 354 */ 355 typedef enum 356 { 357 RCM_FLAG_HSIRDY = 0x001, /*!< HSI Ready Flag */ 358 RCM_FLAG_HSERDY = 0x011, /*!< HSE Ready Flag */ 359 RCM_FLAG_PLL1RDY = 0x019, /*!< PLL1 Ready Flag */ 360 RCM_FLAG_PLL2RDY = 0x01B, /*!< PLL2 Ready Flag */ 361 362 RCM_FLAG_LSERDY = 0x101, /*!< LSE Ready Flag */ 363 364 RCM_FLAG_LSIRDY = 0x201, /*!< LSI Ready Flag */ 365 RCM_FLAG_BORRST = 0x219, /*!< POR/PDR or BOR reset Flag */ 366 RCM_FLAG_PINRST = 0x21A, /*!< PIN reset flag */ 367 RCM_FLAG_PORRST = 0x21B, /*!< POR/PDR reset flag */ 368 RCM_FLAG_SWRST = 0x21C, /*!< Software reset flag */ 369 RCM_FLAG_IWDTRST = 0x21D, /*!< Independent watchdog reset flag */ 370 RCM_FLAG_WWDTRST = 0x21E, /*!< Window watchdog reset flag */ 371 RCM_FLAG_LPRRST = 0x21F, /*!< Low-power reset flag */ 372 } RCM_FLAG_T; 373 374 /**@} end of group RCM_Enumerations*/ 375 376 /** @defgroup RCM_Functions 377 @{ 378 */ 379 380 /* Function description */ 381 382 /* RCM Reset */ 383 void RCM_Reset(void); 384 385 /* HSE clock */ 386 void RCM_ConfigHSE(RCM_HSE_T state); 387 uint8_t RCM_WaitHSEReady(void); 388 389 /* HSI clock */ 390 void RCM_ConfigHSITrim(uint8_t HSITrim); 391 void RCM_EnableHSI(void); 392 void RCM_DisableHSI(void); 393 394 /* LSE and LSI clock */ 395 void RCM_ConfigLSE(RCM_LSE_T state); 396 void RCM_EnableLSI(void); 397 void RCM_DisableLSI(void); 398 399 /* PLL clock */ 400 void RCM_ConfigPLL1(uint32_t pllSelect, uint32_t inputDiv, uint32_t vcoMul, 401 RCM_PLL_SYS_DIV_T sysDiv, uint32_t appDiv); 402 void RCM_EnablePLL1(void); 403 void RCM_DisablePLL1(void); 404 void RCM_ConfigPLL2(uint32_t i2sVcoMul, uint32_t i2sDiv); 405 void RCM_EnablePLL2(void); 406 void RCM_DisablePLL2(void); 407 408 /* Clock Security System */ 409 void RCM_EnableCSS(void); 410 void RCM_DisableCSS(void); 411 412 void RCM_ConfigMCO1(RCM_MCO1_SEL_T mco1Select, RCM_MCO1_DIV_T mco1Div); 413 void RCM_ConfigMCO2(RCM_MCO2_SEL_T mco2Select, RCM_MCO2_DIV_T mco2Div); 414 void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect); 415 RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void); 416 417 /* Config clock prescaler of AHB, APB1, APB2, SDRAM, USB and ADC */ 418 void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv); 419 void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div); 420 void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div); 421 void RCM_ConfigSDRAM(RCM_SDRAM_DIV_T SDRAMDiv); 422 423 /* Reads the clock frequency */ 424 uint32_t RCM_ReadSYSCLKFreq(void); 425 uint32_t RCM_ReadHCLKFreq(void); 426 void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2); 427 428 /* RTC clock */ 429 void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect); 430 void RCM_EnableRTCCLK(void); 431 void RCM_DisableRTCCLK(void); 432 433 /* Backup domain reset */ 434 void RCM_EnableBackupReset(void); 435 void RCM_DisableBackupReset(void); 436 437 void RCM_ConfigI2SCLK(RCM_I2S_CLK_T i2sClkSource); 438 439 /* Enable or disable Periph Clock */ 440 void RCM_EnableAHB1PeriphClock(uint32_t AHB1Periph); 441 void RCM_DisableAHB1PeriphClock(uint32_t AHB1Periph); 442 void RCM_EnableAHB2PeriphClock(uint32_t AHB2Periph); 443 void RCM_DisableAHB2PeriphClock(uint32_t AHB2Periph); 444 void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph); 445 void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph); 446 void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph); 447 void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph); 448 449 /* Enable or disable Periph Reset */ 450 void RCM_EnableAHB1PeriphReset(uint32_t AHB1Periph); 451 void RCM_DisableAHB1PeriphReset(uint32_t AHB1Periph); 452 void RCM_EnableAHB2PeriphReset(uint32_t AHB2Periph); 453 void RCM_DisableAHB2PeriphReset(uint32_t AHB2Periph); 454 void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph); 455 void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph); 456 void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph); 457 void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph); 458 459 /* Enable or disable Periph clock during Low Power (Sleep) mode */ 460 void RCM_EnableAHB1PeriphClockLPMode(uint32_t AHB1Periph); 461 void RCM_DisableAHB1PeriphClockLPMode(uint32_t AHB1Periph); 462 void RCM_EnableAHB2PeriphClockLPMode(uint32_t AHB2Periph); 463 void RCM_DisableAHB2PeriphClockLPMode(uint32_t AHB2Periph); 464 void RCM_EnableAPB1PeriphClockLPMode(uint32_t APB1Periph); 465 void RCM_DisableAPB1PeriphClockLPMode(uint32_t APB1Periph); 466 void RCM_EnableAPB2PeriphClockLPMode(uint32_t APB2Periph); 467 void RCM_DisableAPB2PeriphClockLPMode(uint32_t APB2Periph); 468 469 /* Interrupts and flags */ 470 void RCM_EnableInterrupt(uint32_t interrupt); 471 void RCM_DisableInterrupt(uint32_t interrupt); 472 uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag); 473 void RCM_ClearStatusFlag(void); 474 uint8_t RCM_ReadIntFlag(RCM_INT_T flag); 475 void RCM_ClearIntFlag(uint32_t flag); 476 477 #ifdef __cplusplus 478 } 479 #endif 480 481 #endif /* __APM32F4XX_RCM_H */ 482 483 /**@} end of group RCM_Enumerations */ 484 /**@} end of group RCM_Driver */ 485 /**@} end of group APM32F4xx_StdPeriphDriver */ 486