1 /*! 2 * @file apm32f4xx_smc.h 3 * 4 * @brief This file contains all the functions prototypes for the SMC firmware library 5 * 6 * @version V1.0.2 7 * 8 * @date 2022-06-23 9 * 10 * @attention 11 * 12 * Copyright (C) 2021-2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be usefull and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32F4XX_SMC_H 28 #define __APM32F4XX_SMC_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* Includes */ 35 #include "apm32f4xx.h" 36 37 /** @addtogroup APM32F4xx_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup SMC_Driver 42 @{ 43 */ 44 45 /** @defgroup SMC_Enumerations 46 @{ 47 */ 48 49 /** 50 * @brief SMC NORSRAM Bank 51 */ 52 typedef enum 53 { 54 SMC_BANK1_NORSRAM_1, /*!< SMC Bank1 NOR/SRAM1 */ 55 SMC_BANK1_NORSRAM_2, /*!< SMC Bank1 NOR/SRAM2 */ 56 SMC_BANK1_NORSRAM_3, /*!< SMC Bank1 NOR/SRAM3 */ 57 SMC_BANK1_NORSRAM_4 /*!< SMC Bank1 NOR/SRAM4 */ 58 } SMC_BANK1_NORSRAM_T; 59 60 /** 61 * @brief SMC NAND and PC Card Bank 62 */ 63 typedef enum 64 { 65 SMC_BANK2_NAND, /*!< SMC Bank2 NAND */ 66 SMC_BANK3_NAND, /*!< SMC Bank3 NAND */ 67 SMC_BANK4_PCCARD /*!< SMC Bank4 PCCARD */ 68 } SMC_BANK_NAND_T; 69 70 /** 71 * @brief SMC_Data_Address_Bus_Multiplexing 72 */ 73 typedef enum 74 { 75 SMC_DATA_ADDRESS_MUX_DISABLE, /*!< Disable data address multiplexing */ 76 SMC_DATA_ADDRESS_MUX_ENABLE /*!< Enable data address multiplexing */ 77 } SMC_DATA_ADDRESS_MUX_T; 78 79 /** 80 * @brief SMC_Memory_Type 81 */ 82 typedef enum 83 { 84 SMC_MEMORY_TYPE_SRAM, /*!< SRAM memory */ 85 SMC_MEMORY_TYPE_PSRAM, /*!< PSRAM memory */ 86 SMC_MEMORY_TYPE_NOR /*!< NORFlash memory */ 87 } SMC_MEMORY_TYPE_T; 88 89 /** 90 * @brief SMC_Data_Width 91 */ 92 typedef enum 93 { 94 SMC_MEMORY_DATA_WIDTH_8BIT, /*!< Set memory data width to 8-bit */ 95 SMC_MEMORY_DATA_WIDTH_16BIT /*!< Set memory data width to 16-bit */ 96 } SMC_MEMORY_DATA_WIDTH_T; 97 98 /** 99 * @brief SMC_Burst_Access_Mode 100 */ 101 typedef enum 102 { 103 SMC_BURST_ACCESS_MODE_DISABLE, /*!< Disable burst access mode */ 104 SMC_BURST_ACCESS_MODE_ENABLE /*!< Enable burst access mode */ 105 } SMC_BURST_ACCESS_MODE_T; 106 107 /** 108 * @brief SMC_AsynchronousWait 109 */ 110 typedef enum 111 { 112 SMC_ASYNCHRONOUS_WAIT_DISABLE, /*!< Disable asynchronous wait */ 113 SMC_ASYNCHRONOUS_WAIT_ENABLE /*!< Enable asynchronous wait */ 114 } SMC_ASYNCHRONOUS_WAIT_T; 115 116 /** 117 * @brief SMC_Wait_Signal_Polarity 118 */ 119 typedef enum 120 { 121 SMC_WAIT_SIGNAL_POLARITY_LOW, /*!< Set low polarity valid */ 122 SMC_WAIT_SIGNAL_POLARITY_HIGH /*!< Set high polarity valid */ 123 } SMC_WAIT_SIGNAL_POLARITY_T; 124 125 /** 126 * @brief SMC Wrapped burst Mode 127 */ 128 typedef enum 129 { 130 SMC_WRAP_MODE_DISABLE, /*!< Disable wrapped burst mode */ 131 SMC_WRAP_MODE_ENABLE /*!< Enable wrapped burst mode */ 132 } SMC_WRAP_MODE_T; 133 134 /** 135 * @brief SMC Wait Timing 136 */ 137 typedef enum 138 { 139 SMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT_STATE, /*!< Set wait active before wait state */ 140 SMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT_STATE /*!< Set wait active during wait state */ 141 } SMC_WAIT_SIGNAL_ACTIVE_T; 142 143 /** 144 * @brief SMC Write Operation 145 */ 146 typedef enum 147 { 148 SMC_WRITE_OPERATION_DISABLE, /*!< Disable write operation */ 149 SMC_WRITE_OPERATION_ENABLE /*!< Enable write operation */ 150 } SMC_WRITE_OPERATION_T; 151 152 /** 153 * @brief SMC Wait Signal 154 */ 155 typedef enum 156 { 157 SMC_WAITE_SIGNAL_DISABLE, /*!< Disable wait signal */ 158 SMC_WAITE_SIGNAL_ENABLE /*!< Enable wait signal */ 159 } SMC_WAITE_SIGNAL_T; 160 161 /** 162 * @brief SMC Extended Mode 163 */ 164 typedef enum 165 { 166 SMC_EXTENDEN_MODE_DISABLE, /*!< Disable extended mode */ 167 SMC_EXTENDEN_MODE_ENABLE /*!< Enable extended mode */ 168 } SMC_EXTENDEN_MODE_T; 169 170 /** 171 * @brief SMC Write Burst 172 */ 173 typedef enum 174 { 175 SMC_WRITE_BURST_DISABLE, /*!< Disable write PSRAM burst */ 176 SMC_WRITE_BURST_ENABLE /*!< Enable write PSRAM burst */ 177 } SMC_WRITE_BURST_T; 178 179 /** 180 * @brief SMC WAIT FEATURE 181 */ 182 typedef enum 183 { 184 SMC_WAIT_FEATURE_DISABLE, /*!< Disable wait feature */ 185 SMC_WAIT_FEATURE_ENABLE /*!< Enable wait feature */ 186 } SMC_WAIT_FEATURE_T; 187 188 /** 189 * @brief SMC ECC 190 */ 191 typedef enum 192 { 193 SMC_ECC_DISABLE, /*!< Disable ECC */ 194 SMC_ECC_ENABLE /*!< Enable ECC */ 195 } SMC_ECC_T; 196 197 /** 198 * @brief SMC ECC Page Size 199 */ 200 typedef enum 201 { 202 SMC_ECC_PAGE_SIZE_BYTE_256, /*!< ECC page size = 256 bytes */ 203 SMC_ECC_PAGE_SIZE_BYTE_512, /*!< ECC page size = 512 bytes */ 204 SMC_ECC_PAGE_SIZE_BYTE_1024, /*!< ECC page size = 1024 bytes */ 205 SMC_ECC_PAGE_SIZE_BYTE_2048, /*!< ECC page size = 2048 bytes */ 206 SMC_ECC_PAGE_SIZE_BYTE_4096, /*!< ECC page size = 4096 bytes */ 207 SMC_ECC_PAGE_SIZE_BYTE_8192 /*!< ECC page size = 8192 bytes */ 208 } SMC_ECC_PAGE_SIZE_BYTE_T; 209 210 /** 211 * @brief SMC Access Mode 212 */ 213 typedef enum 214 { 215 SMC_ACCESS_MODE_A, /*!< Access mode A */ 216 SMC_ACCESS_MODE_B, /*!< Access mode B */ 217 SMC_ACCESS_MODE_C, /*!< Access mode C */ 218 SMC_ACCESS_MODE_D /*!< Access mode D */ 219 } SMC_ACCESS_MODE_T; 220 221 /** 222 * @brief SMC Interrupt sources 223 */ 224 typedef enum 225 { 226 SMC_INT_EDGE_RISING = 0x00000008, /*!< Rising edge detection interrupt */ 227 SMC_INT_LEVEL_HIGH = 0x00000010, /*!< High level detection interrupt */ 228 SMC_INT_EDGE_FALLING = 0x00000020 /*!< Falling edge detection interrupt */ 229 } SMC_INT_T; 230 231 /** 232 * @brief SMC Flags 233 */ 234 typedef enum 235 { 236 SMC_FLAG_EDGE_RISING = 0x00000001, /*!< Rising egde detection Flag */ 237 SMC_FLAG_LEVEL_HIGH = 0x00000002, /*!< High level detection Flag */ 238 SMC_FLAG_EDGE_FALLING = 0x00000004, /*!< Falling egde detection Flag */ 239 SMC_FLAG_FIFO_EMPTY = 0x00000040 /*!< FIFO empty Flag */ 240 } SMC_FLAG_T; 241 242 /**@} end of group SMC_Enumerations*/ 243 244 /** @addtogroup SMC_Structure Data Structure 245 @{ 246 */ 247 248 /** 249 * @brief Timing parameters for NOR/SRAM Banks 250 */ 251 typedef struct 252 { 253 uint8_t addressSetupTime; /*!< Set address setup time */ 254 uint8_t addressHodeTime; /*!< Set address-hold setup time */ 255 uint8_t dataSetupTime; /*!< Set data setup time */ 256 uint8_t busTurnaroundTime; /*!< Set bus turnaround time */ 257 uint8_t clockDivision; /*!< Set clock divide radio */ 258 uint8_t dataLatency; /*!< Set data latency */ 259 SMC_ACCESS_MODE_T accessMode; /*!< Set access mode */ 260 } SMC_NORSRAMTimingConfig_T; 261 262 /** 263 * @brief SMC NOR/SRAM Config structure 264 */ 265 typedef struct 266 { 267 SMC_BANK1_NORSRAM_T bank; /*!< NORSRAM bank selection */ 268 SMC_DATA_ADDRESS_MUX_T dataAddressMux; /*!< Data address bus multiplexing selection */ 269 SMC_MEMORY_TYPE_T memoryType; /*!< Memory type selection */ 270 SMC_MEMORY_DATA_WIDTH_T memoryDataWidth; /*!< Data width selection */ 271 SMC_BURST_ACCESS_MODE_T burstAcceesMode; /*!< Set burst access mode */ 272 SMC_ASYNCHRONOUS_WAIT_T asynchronousWait; /*!< Set asynchronous wait */ 273 SMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity; /*!< Set wait signal polarity */ 274 SMC_WRAP_MODE_T wrapMode; /*!< Set wrapped burst mode */ 275 SMC_WAIT_SIGNAL_ACTIVE_T waitSignalActive; /*!< Set wait timing */ 276 SMC_WRITE_OPERATION_T writeOperation; /*!< Set write operation */ 277 SMC_WAITE_SIGNAL_T waiteSignal; /*!< Set wait signal */ 278 SMC_EXTENDEN_MODE_T extendedMode; /*!< Set extended mode */ 279 SMC_WRITE_BURST_T writeBurst; /*!< Set write burst */ 280 SMC_NORSRAMTimingConfig_T* readWriteTimingStruct; /*!< Read and write timing */ 281 SMC_NORSRAMTimingConfig_T* writeTimingStruct; /*!< Write timing */ 282 } SMC_NORSRAMConfig_T; 283 284 /** 285 * @brief Timing parameters for NAND and PCCARD Banks 286 */ 287 typedef struct 288 { 289 uint8_t setupTime; /*!< Set setup address time( 0x01 ~ 0xFE ) */ 290 uint8_t waitSetupTime; /*!< Set assert the command time ( 0x01 ~ 0xFE ) */ 291 uint8_t holdSetupTime; /*!< Set hold address time ( 0x01 ~ 0xFE ) */ 292 uint8_t HiZSetupTime; /*!< Set the time of keep in HiZ ( 0x00 ~ 0xFE ) */ 293 } SMC_NAND_PCCARDTimingConfig_T; 294 295 /** 296 * @brief SMC NAND Config structure 297 */ 298 typedef struct 299 { 300 SMC_BANK_NAND_T bank; /*!< SMC NAND and PC Card Bank */ 301 SMC_WAIT_FEATURE_T waitFeature; /*!< Set wait feature */ 302 SMC_MEMORY_DATA_WIDTH_T memoryDataWidth; /*!< Data width selection */ 303 SMC_ECC_T ECC; /*!< Set ECC */ 304 SMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize; /*!< Set ECC page size */ 305 uint8_t TCLRSetupTime; /*!< Set the delay time of CLE to RE */ 306 uint8_t TARSetupTime; /*!< Set the delay time of ALE to RE */ 307 SMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct; /*!< Common space timing */ 308 SMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct; /*!< Attribute space timing */ 309 } SMC_NANDConfig_T; 310 311 /** 312 * @brief SMC PCCARD Config structure 313 */ 314 typedef struct 315 { 316 SMC_WAIT_FEATURE_T waitFeature; /*!< Set wait feature */ 317 uint32_t TCLRSetupTime; /*!< Set the delay time of CLE to RE */ 318 uint32_t TARSetupTime; /*!< Set the delay time of ALE to RE */ 319 SMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct; /*!< Common space timing */ 320 SMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct; /*!< Attribute space timing */ 321 SMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct; /*!< IO space timing */ 322 } SMC_PCCARDConfig_T; 323 324 /**@} end of group SMC_Structure*/ 325 326 /** @defgroup SMC_Functions 327 @{ 328 */ 329 330 /* SMC reset */ 331 void SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank); 332 void SMC_ResetNAND(SMC_BANK_NAND_T bank); 333 void SMC_ResetPCCard(void); 334 335 /* SMC Configuration */ 336 void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig); 337 void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig); 338 void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig); 339 void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T* smcNORSRAMConfig); 340 void SMC_ConfigNANDStructInit(SMC_NANDConfig_T* smcNANDConfig); 341 void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T* smcPCCardConfig); 342 343 /* SMC bank control */ 344 void SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank); 345 void SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank); 346 void SMC_EnableNAND(SMC_BANK_NAND_T bank); 347 void SMC_DisableNAND(SMC_BANK_NAND_T bank); 348 void SMC_EnablePCCARD(void); 349 void SMC_DisablePCCARD(void); 350 void SMC_EnableNANDECC(SMC_BANK_NAND_T bank); 351 void SMC_DisableNANDECC(SMC_BANK_NAND_T bank); 352 uint32_t SMC_ReadECC(SMC_BANK_NAND_T bank); 353 354 /* Interrupt and flag */ 355 void SMC_EnableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt); 356 void SMC_DisableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt); 357 uint16_t SMC_ReadStatusFlag(SMC_BANK_NAND_T bank, SMC_FLAG_T flag); 358 void SMC_ClearStatusFlag(SMC_BANK_NAND_T bank, uint32_t flag); 359 uint16_t SMC_ReadIntFlag(SMC_BANK_NAND_T bank, SMC_INT_T flag); 360 void SMC_ClearIntFlag(SMC_BANK_NAND_T bank, uint32_t flag); 361 362 #ifdef __cplusplus 363 } 364 #endif 365 366 #endif /* __APM32F4XX_SMC_H */ 367 368 /**@} end of group SMC_Enumerations */ 369 /**@} end of group SMC_Driver */ 370 /**@} end of group APM32F4xx_StdPeriphDriver */ 371