1 /*! 2 * @file apm32s10x_dma.h 3 * 4 * @brief This file contains all the functions prototypes for the DMA firmware library 5 * 6 * @version V1.0.1 7 * 8 * @date 2022-12-31 9 * 10 * @attention 11 * 12 * Copyright (C) 2022-2023 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be usefull and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32S10X_DMA_H 28 #define __APM32S10X_DMA_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* Includes */ 35 #include "apm32s10x.h" 36 37 /** @addtogroup APM32S10x_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup DMA_Driver DMA Driver 42 @{ 43 */ 44 45 /** @defgroup DMA_Enumerations Enumerations 46 @{ 47 */ 48 49 /** 50 * @brief DMA Transmission direction 51 */ 52 typedef enum 53 { 54 DMA_DIR_PERIPHERAL_SRC, 55 DMA_DIR_PERIPHERAL_DST 56 } DMA_DIR_T; 57 58 /** 59 * @brief DMA Peripheral address increment 60 */ 61 typedef enum 62 { 63 DMA_PERIPHERAL_INC_DISABLE, 64 DMA_PERIPHERAL_INC_ENABLE 65 } DMA_PERIPHERAL_INC_T; 66 67 /** 68 * @brief DMA Memory address increment 69 */ 70 typedef enum 71 { 72 DMA_MEMORY_INC_DISABLE, 73 DMA_MEMORY_INC_ENABLE 74 } DMA_MEMORY_INC_T; 75 76 /** 77 * @brief DMA Peripheral Data Size 78 */ 79 typedef enum 80 { 81 DMA_PERIPHERAL_DATA_SIZE_BYTE, 82 DMA_PERIPHERAL_DATA_SIZE_HALFWORD, 83 DMA_PERIPHERAL_DATA_SIZE_WOED 84 } DMA_PERIPHERAL_DATA_SIZE_T; 85 86 /** 87 * @brief DMA Memory Data Size 88 */ 89 typedef enum 90 { 91 DMA_MEMORY_DATA_SIZE_BYTE, 92 DMA_MEMORY_DATA_SIZE_HALFWORD, 93 DMA_MEMORY_DATA_SIZE_WOED 94 } DMA_MEMORY_DATA_SIZE_T; 95 96 /** 97 * @brief DMA Mode 98 */ 99 typedef enum 100 { 101 DMA_MODE_NORMAL, 102 DMA_MODE_CIRCULAR 103 } DMA_LOOP_MODE_T; 104 105 /** 106 * @brief DMA priority level 107 */ 108 typedef enum 109 { 110 DMA_PRIORITY_LOW, 111 DMA_PRIORITY_MEDIUM, 112 DMA_PRIORITY_HIGH, 113 DMA_PRIORITY_VERYHIGH 114 } DMA_PRIORITY_T; 115 116 /** 117 * @brief DMA Memory to Memory 118 */ 119 typedef enum 120 { 121 DMA_M2MEN_DISABLE, 122 DMA_M2MEN_ENABLE 123 } DMA_M2MEN_T; 124 125 /** 126 * @brief DMA interrupt 127 */ 128 typedef enum 129 { 130 DMA_INT_TC = 0x00000002, 131 DMA_INT_HT = 0x00000004, 132 DMA_INT_TERR = 0x00000008 133 } DMA_INT_T; 134 135 /** 136 * @brief DMA Flag 137 */ 138 typedef enum 139 { 140 DMA1_FLAG_GINT1 = 0x00000001, 141 DMA1_FLAG_TC1 = 0x00000002, 142 DMA1_FLAG_HT1 = 0x00000004, 143 DMA1_FLAG_TERR1 = 0x00000008, 144 DMA1_FLAG_GINT2 = 0x00000010, 145 DMA1_FLAG_TC2 = 0x00000020, 146 DMA1_FLAG_HT2 = 0x00000040, 147 DMA1_FLAG_TERR2 = 0x00000080, 148 DMA1_FLAG_GINT3 = 0x00000100, 149 DMA1_FLAG_TC3 = 0x00000200, 150 DMA1_FLAG_HT3 = 0x00000400, 151 DMA1_FLAG_TERR3 = 0x00000800, 152 DMA1_FLAG_GINT4 = 0x00001000, 153 DMA1_FLAG_TC4 = 0x00002000, 154 DMA1_FLAG_HT4 = 0x00004000, 155 DMA1_FLAG_TERR4 = 0x00008000, 156 DMA1_FLAG_GINT5 = 0x00010000, 157 DMA1_FLAG_TC5 = 0x00020000, 158 DMA1_FLAG_HT5 = 0x00040000, 159 DMA1_FLAG_TERR5 = 0x00080000, 160 DMA1_FLAG_GINT6 = 0x00100000, 161 DMA1_FLAG_TC6 = 0x00200000, 162 DMA1_FLAG_HT6 = 0x00400000, 163 DMA1_FLAG_TERR6 = 0x00800000, 164 DMA1_FLAG_GINT7 = 0x01000000, 165 DMA1_FLAG_TC7 = 0x02000000, 166 DMA1_FLAG_HT7 = 0x04000000, 167 DMA1_FLAG_TERR7 = 0x08000000, 168 } DMA_FLAG_T; 169 170 /** 171 * @brief DMA Interrupt Flag 172 */ 173 typedef enum 174 { 175 DMA1_INT_FLAG_GINT1 = 0x00000001, 176 DMA1_INT_FLAG_TC1 = 0x00000002, 177 DMA1_INT_FLAG_HT1 = 0x00000004, 178 DMA1_INT_FLAG_TERR1 = 0x00000008, 179 DMA1_INT_FLAG_GINT2 = 0x00000010, 180 DMA1_INT_FLAG_TC2 = 0x00000020, 181 DMA1_INT_FLAG_HT2 = 0x00000040, 182 DMA1_INT_FLAG_TERR2 = 0x00000080, 183 DMA1_INT_FLAG_GINT3 = 0x00000100, 184 DMA1_INT_FLAG_TC3 = 0x00000200, 185 DMA1_INT_FLAG_HT3 = 0x00000400, 186 DMA1_INT_FLAG_TERR3 = 0x00000800, 187 DMA1_INT_FLAG_GINT4 = 0x00001000, 188 DMA1_INT_FLAG_TC4 = 0x00002000, 189 DMA1_INT_FLAG_HT4 = 0x00004000, 190 DMA1_INT_FLAG_TERR4 = 0x00008000, 191 DMA1_INT_FLAG_GINT5 = 0x00010000, 192 DMA1_INT_FLAG_TC5 = 0x00020000, 193 DMA1_INT_FLAG_HT5 = 0x00040000, 194 DMA1_INT_FLAG_TERR5 = 0x00080000, 195 DMA1_INT_FLAG_GINT6 = 0x00100000, 196 DMA1_INT_FLAG_TC6 = 0x00200000, 197 DMA1_INT_FLAG_HT6 = 0x00400000, 198 DMA1_INT_FLAG_TERR6 = 0x00800000, 199 DMA1_INT_FLAG_GINT7 = 0x01000000, 200 DMA1_INT_FLAG_TC7 = 0x02000000, 201 DMA1_INT_FLAG_HT7 = 0x04000000, 202 DMA1_INT_FLAG_TERR7 = 0x08000000, 203 } DMA_INT_FLAG_T; 204 205 /**@} end of group DMA_Enumerations */ 206 207 /** @defgroup DMA_Structures Structures 208 @{ 209 */ 210 211 /** 212 * @brief DMA Configure structure definition 213 */ 214 typedef struct 215 { 216 uint32_t peripheralBaseAddr; 217 uint32_t memoryBaseAddr; 218 DMA_DIR_T dir; 219 uint32_t bufferSize; 220 DMA_PERIPHERAL_INC_T peripheralInc; 221 DMA_MEMORY_INC_T memoryInc; 222 DMA_PERIPHERAL_DATA_SIZE_T peripheralDataSize; 223 DMA_MEMORY_DATA_SIZE_T memoryDataSize; 224 DMA_LOOP_MODE_T loopMode; 225 DMA_PRIORITY_T priority; 226 DMA_M2MEN_T M2M; 227 } DMA_Config_T; 228 229 /**@} end of group DMA_Structures */ 230 231 /** @defgroup DMA_Functions Functions 232 @{ 233 */ 234 235 /* Reset and configuration */ 236 void DMA_Reset(DMA_Channel_T* channel); 237 void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig); 238 void DMA_ConfigStructInit(DMA_Config_T* dmaConfig); 239 void DMA_Enable(DMA_Channel_T* channel); 240 void DMA_Disable(DMA_Channel_T* channel); 241 242 /* Data number */ 243 void DMA_ConfigDataNumber(DMA_Channel_T* channel, uint16_t dataNumber); 244 uint16_t DMA_ReadDataNumber(DMA_Channel_T* channel); 245 246 /* Interrupt and flag */ 247 void DMA_EnableInterrupt(DMA_Channel_T* channel, uint32_t interrupt); 248 void DMA_DisableInterrupt(DMA_Channel_T* channel, uint32_t interrupt); 249 uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag); 250 void DMA_ClearStatusFlag(uint32_t flag); 251 uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag); 252 void DMA_ClearIntFlag(uint32_t flag); 253 254 /**@} end of group DMA_Functions */ 255 /**@} end of group DMA_Driver */ 256 /**@} end of group APM32S10x_StdPeriphDriver */ 257 258 #ifdef __cplusplus 259 } 260 #endif 261 262 #endif /* __APM32S10X_DMA_H */ 263