1 /*! 2 * @file apm32s10x_rcm.h 3 * 4 * @brief This file contains all the functions prototypes for the RCM firmware library 5 * 6 * @version V1.0.1 7 * 8 * @date 2022-12-31 9 * 10 * @attention 11 * 12 * Copyright (C) 2022-2023 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be usefull and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32S10X_RCM_H 28 #define __APM32S10X_RCM_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* Includes */ 35 #include "apm32s10x.h" 36 37 /** @addtogroup APM32S10x_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup RCM_Driver RCM Driver 42 @{ 43 */ 44 45 /** @defgroup RCM_Enumerations Enumerations 46 @{ 47 */ 48 49 /** 50 * @brief HSE state 51 */ 52 typedef enum 53 { 54 RCM_HSE_CLOSE, 55 RCM_HSE_OPEN, 56 RCM_HSE_BYPASS 57 } RCM_HSE_T; 58 59 /** 60 * @brief PLL multiplication factor 61 */ 62 typedef enum 63 { 64 RCM_PLLMF_2, 65 RCM_PLLMF_3, 66 RCM_PLLMF_4, 67 RCM_PLLMF_5, 68 RCM_PLLMF_6, 69 RCM_PLLMF_7, 70 RCM_PLLMF_8, 71 RCM_PLLMF_9, 72 RCM_PLLMF_10, 73 RCM_PLLMF_11, 74 RCM_PLLMF_12, 75 RCM_PLLMF_13, 76 RCM_PLLMF_14, 77 RCM_PLLMF_15, 78 RCM_PLLMF_16 79 } RCM_PLLMF_T; 80 81 /** 82 * @brief System clock select 83 */ 84 typedef enum 85 { 86 RCM_SYSCLK_SEL_HSI, 87 RCM_SYSCLK_SEL_HSE, 88 RCM_SYSCLK_SEL_PLL 89 } RCM_SYSCLK_SEL_T; 90 91 /** 92 * @brief AHB divider Number 93 */ 94 typedef enum 95 { 96 RCM_AHB_DIV_1 = 7, 97 RCM_AHB_DIV_2, 98 RCM_AHB_DIV_4, 99 RCM_AHB_DIV_8, 100 RCM_AHB_DIV_16, 101 RCM_AHB_DIV_64, 102 RCM_AHB_DIV_128, 103 RCM_AHB_DIV_256, 104 RCM_AHB_DIV_512 105 } RCM_AHB_DIV_T; 106 107 /** 108 * @brief APB divider Number 109 */ 110 typedef enum 111 { 112 RCM_APB_DIV_1 = 3, 113 RCM_APB_DIV_2, 114 RCM_APB_DIV_4, 115 RCM_APB_DIV_8, 116 RCM_APB_DIV_16 117 } RCM_APB_DIV_T; 118 119 /** 120 * @brief USB divider Number 121 */ 122 typedef enum 123 { 124 RCM_USB_DIV_1_5, 125 RCM_USB_DIV_1, 126 RCM_USB_DIV_2, 127 } RCM_USB_DIV_T; 128 129 /** 130 * @brief FPU divider Number 131 */ 132 typedef enum 133 { 134 RCM_FPU_DIV_1, 135 RCM_FPU_DIV_2 136 } RCM_FPU_DIV_T; 137 138 /** 139 * @brief ADC divider Number 140 */ 141 typedef enum 142 { 143 RCM_PCLK2_DIV_2, 144 RCM_PCLK2_DIV_4, 145 RCM_PCLK2_DIV_6, 146 RCM_PCLK2_DIV_8 147 } RCM_PCLK2_DIV_T; 148 149 /** 150 * @brief LSE State 151 */ 152 typedef enum 153 { 154 RCM_LSE_CLOSE, 155 RCM_LSE_OPEN, 156 RCM_LSE_BYPASS 157 } RCM_LSE_T; 158 159 /** 160 * @brief RTC clock select 161 */ 162 typedef enum 163 { 164 RCM_RTCCLK_LSE = 1, 165 RCM_RTCCLK_LSI, 166 RCM_RTCCLK_HSE_DIV_128 167 } RCM_RTCCLK_T; 168 169 /** 170 * @brief Clock output control 171 */ 172 typedef enum 173 { 174 RCM_MCOCLK_NO_CLOCK = 3, 175 RCM_MCOCLK_SYSCLK, 176 RCM_MCOCLK_HSI, 177 RCM_MCOCLK_HSE, 178 RCM_MCOCLK_PLLCLK_DIV_2 179 } RCM_MCOCLK_T; 180 181 /** 182 * @brief PLL entry clock select 183 */ 184 typedef enum 185 { 186 RCM_PLLSEL_HSI_DIV_2 = 0, 187 RCM_PLLSEL_HSE = 1, 188 RCM_PLLSEL_HSE_DIV2 = 3, 189 } RCM_PLLSEL_T; 190 191 /** 192 * @brief RCM Interrupt Source 193 */ 194 typedef enum 195 { 196 RCM_INT_LSIRDY = BIT0, /*!< LSI ready interrupt */ 197 RCM_INT_LSERDY = BIT1, /*!< LSE ready interrupt */ 198 RCM_INT_HSIRDY = BIT2, /*!< HSI ready interrupt */ 199 RCM_INT_HSERDY = BIT3, /*!< HSE ready interrupt */ 200 RCM_INT_PLLRDY = BIT4, /*!< PLL ready interrupt */ 201 RCM_INT_CSS = BIT7 /*!< Clock security system interrupt */ 202 } RCM_INT_T; 203 204 /** 205 * @brief AHB peripheral 206 */ 207 typedef enum 208 { 209 RCM_AHB_PERIPH_DMA1 = BIT0, 210 RCM_AHB_PERIPH_SRAM = BIT2, 211 RCM_AHB_PERIPH_FPU = BIT3, 212 RCM_AHB_PERIPH_FMC = BIT4, 213 RCM_AHB_PERIPH_QSPI = BIT5, 214 RCM_AHB_PERIPH_CRC = BIT6 215 } RCM_AHB_PERIPH_T; 216 217 /** 218 * @brief AHB2 peripheral 219 */ 220 typedef enum 221 { 222 RCM_APB2_PERIPH_AFIO = BIT0, 223 RCM_APB2_PERIPH_GPIOA = BIT2, 224 RCM_APB2_PERIPH_GPIOB = BIT3, 225 RCM_APB2_PERIPH_GPIOC = BIT4, 226 RCM_APB2_PERIPH_GPIOD = BIT5, 227 RCM_APB2_PERIPH_GPIOE = BIT6, 228 RCM_APB2_PERIPH_ADC1 = BIT9, 229 RCM_APB2_PERIPH_ADC2 = BIT10, 230 RCM_APB2_PERIPH_TMR1 = BIT11, 231 RCM_APB2_PERIPH_SPI1 = BIT12, 232 RCM_APB2_PERIPH_USART1 = BIT14 233 } RCM_APB2_PERIPH_T; 234 235 /** 236 * @brief AHB1 peripheral 237 */ 238 typedef enum 239 { 240 RCM_APB1_PERIPH_TMR2 = BIT0, 241 RCM_APB1_PERIPH_TMR3 = BIT1, 242 RCM_APB1_PERIPH_TMR4 = BIT2, 243 RCM_APB1_PERIPH_WWDT = BIT11, 244 RCM_APB1_PERIPH_SPI2 = BIT14, 245 RCM_APB1_PERIPH_USART2 = BIT17, 246 RCM_APB1_PERIPH_USART3 = BIT18, 247 RCM_APB1_PERIPH_I2C1 = BIT21, 248 RCM_APB1_PERIPH_I2C2 = BIT22, 249 RCM_APB1_PERIPH_USB = BIT23, 250 RCM_APB1_PERIPH_CAN1 = BIT25, 251 RCM_APB1_PERIPH_CAN2 = BIT26, 252 RCM_APB1_PERIPH_BAKR = BIT27, 253 RCM_APB1_PERIPH_PMU = BIT28 254 } RCM_APB1_PERIPH_T; 255 256 /** 257 * @brief RCM FLAG define 258 */ 259 typedef enum 260 { 261 RCM_FLAG_HSIRDY = 0x001, /*!< HSI Ready Flag */ 262 RCM_FLAG_HSERDY = 0x011, /*!< HSE Ready Flag */ 263 RCM_FLAG_PLLRDY = 0x019, /*!< PLL Ready Flag */ 264 RCM_FLAG_LSERDY = 0x101, /*!< LSE Ready Flag */ 265 RCM_FLAG_LSIRDY = 0x201, /*!< LSI Ready Flag */ 266 RCM_FLAG_PINRST = 0x21A, /*!< PIN reset flag */ 267 RCM_FLAG_PORRST = 0x21B, /*!< POR/PDR reset flag */ 268 RCM_FLAG_SWRST = 0x21C, /*!< Software reset flag */ 269 RCM_FLAG_IWDTRST = 0x21D, /*!< Independent watchdog reset flag */ 270 RCM_FLAG_WWDTRST = 0x21E, /*!< Window watchdog reset flag */ 271 RCM_FLAG_LPRRST = 0x21F /*!< Low-power reset flag */ 272 } RCM_FLAG_T; 273 274 /**@} end of group RCM_Enumerations */ 275 276 /** @defgroup RCM_Functions Functions 277 @{ 278 */ 279 280 /* Function description */ 281 282 /* RCM Reset */ 283 void RCM_Reset(void); 284 285 /* HSE clock */ 286 void RCM_ConfigHSE(RCM_HSE_T state); 287 uint8_t RCM_WaitHSEReady(void); 288 289 /* HSI clock */ 290 void RCM_ConfigHSITrim(uint8_t HSITrim); 291 void RCM_EnableHSI(void); 292 void RCM_DisableHSI(void); 293 294 /* LSE and LSI clock */ 295 void RCM_ConfigLSE(RCM_LSE_T state); 296 void RCM_EnableLSI(void); 297 void RCM_DisableLSI(void); 298 299 /* PLL clock */ 300 void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf); 301 void RCM_EnablePLL(void); 302 void RCM_DisablePLL(void); 303 304 /* Clock Security System */ 305 void RCM_EnableCSS(void); 306 void RCM_DisableCSS(void); 307 308 void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock); 309 void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect); 310 RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void); 311 312 /* Config clock prescaler of AHB, APB1, APB2, USB and ADC */ 313 void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv); 314 void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div); 315 void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div); 316 void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv); 317 void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv); 318 void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv); 319 320 /* RTC clock */ 321 void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect); 322 void RCM_EnableRTCCLK(void); 323 void RCM_DisableRTCCLK(void); 324 325 /* Reads the clock frequency */ 326 uint32_t RCM_ReadSYSCLKFreq(void); 327 uint32_t RCM_ReadHCLKFreq(void); 328 void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2); 329 uint32_t RCM_ReadADCCLKFreq(void); 330 331 /* Enable or disable Periph Clock */ 332 void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph); 333 void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph); 334 void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph); 335 void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph); 336 void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph); 337 void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph); 338 339 /* Enable or disable Periph Reset */ 340 void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph); 341 void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph); 342 void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph); 343 void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph); 344 345 /* Backup domain reset */ 346 void RCM_EnableBackupReset(void); 347 void RCM_DisableBackupReset(void); 348 349 /* Interrupts and flags */ 350 void RCM_EnableInterrupt(uint32_t interrupt); 351 void RCM_DisableInterrupt(uint32_t interrupt); 352 uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag); 353 void RCM_ClearStatusFlag(void); 354 uint8_t RCM_ReadIntFlag(RCM_INT_T flag); 355 void RCM_ClearIntFlag(uint32_t flag); 356 357 /**@} end of group RCM_Functions */ 358 /**@} end of group RCM_Driver */ 359 /**@} end of group APM32S10x_StdPeriphDriver */ 360 361 #ifdef __cplusplus 362 } 363 #endif 364 365 #endif /* __APM32S10X_RCM_H */ 366