1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2011-01-13     weety      first version
9  */
10 
11 #ifndef AT91_RSTC_H
12 #define AT91_RSTC_H
13 
14 #ifdef __cplusplus
15 extern "C" {
16 #endif
17 
18 #define AT91_RSTC_CR        (AT91_RSTC + 0x00)  /* Reset Controller Control Register */
19 #define     AT91_RSTC_PROCRST   (1 << 0)        /* Processor Reset */
20 #define     AT91_RSTC_PERRST    (1 << 2)        /* Peripheral Reset */
21 #define     AT91_RSTC_EXTRST    (1 << 3)        /* External Reset */
22 #define     AT91_RSTC_KEY       (0xa5 << 24)        /* KEY Password */
23 
24 #define AT91_RSTC_SR        (AT91_RSTC + 0x04)  /* Reset Controller Status Register */
25 #define     AT91_RSTC_URSTS     (1 << 0)        /* User Reset Status */
26 #define     AT91_RSTC_RSTTYP    (7 << 8)        /* Reset Type */
27 #define         AT91_RSTC_RSTTYP_GENERAL    (0 << 8)
28 #define         AT91_RSTC_RSTTYP_WAKEUP     (1 << 8)
29 #define         AT91_RSTC_RSTTYP_WATCHDOG   (2 << 8)
30 #define         AT91_RSTC_RSTTYP_SOFTWARE   (3 << 8)
31 #define         AT91_RSTC_RSTTYP_USER   (4 << 8)
32 #define     AT91_RSTC_NRSTL     (1 << 16)       /* NRST Pin Level */
33 #define     AT91_RSTC_SRCMP     (1 << 17)       /* Software Reset Command in Progress */
34 
35 #define AT91_RSTC_MR        (AT91_RSTC + 0x08)  /* Reset Controller Mode Register */
36 #define     AT91_RSTC_URSTEN    (1 << 0)        /* User Reset Enable */
37 #define     AT91_RSTC_URSTIEN   (1 << 4)        /* User Reset Interrupt Enable */
38 #define     AT91_RSTC_ERSTL     (0xf << 8)      /* External Reset Length */
39 
40 #ifdef __cplusplus
41 }
42 #endif
43 
44 #endif
45 
46