1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2011-01-13 weety first version 9 */ 10 11 #ifndef AT91_SERIAL_H 12 #define AT91_SERIAL_H 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #define AT91_US_CR 0x00 /* Control Register */ 19 #define AT91_US_RSTRX (1 << 2) /* Reset Receiver */ 20 #define AT91_US_RSTTX (1 << 3) /* Reset Transmitter */ 21 #define AT91_US_RXEN (1 << 4) /* Receiver Enable */ 22 #define AT91_US_RXDIS (1 << 5) /* Receiver Disable */ 23 #define AT91_US_TXEN (1 << 6) /* Transmitter Enable */ 24 #define AT91_US_TXDIS (1 << 7) /* Transmitter Disable */ 25 #define AT91_US_RSTSTA (1 << 8) /* Reset Status Bits */ 26 #define AT91_US_STTBRK (1 << 9) /* Start Break */ 27 #define AT91_US_STPBRK (1 << 10) /* Stop Break */ 28 #define AT91_US_STTTO (1 << 11) /* Start Time-out */ 29 #define AT91_US_SENDA (1 << 12) /* Send Address */ 30 #define AT91_US_RSTIT (1 << 13) /* Reset Iterations */ 31 #define AT91_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */ 32 #define AT91_US_RETTO (1 << 15) /* Rearm Time-out */ 33 #define AT91_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */ 34 #define AT91_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */ 35 #define AT91_US_RTSEN (1 << 18) /* Request To Send Enable */ 36 #define AT91_US_RTSDIS (1 << 19) /* Request To Send Disable */ 37 38 #define AT91_US_MR 0x04 /* Mode Register */ 39 #define AT91_US_USMODE (0xf << 0) /* Mode of the USART */ 40 #define AT91_US_USMODE_NORMAL 0 41 #define AT91_US_USMODE_RS485 1 42 #define AT91_US_USMODE_HWHS 2 43 #define AT91_US_USMODE_MODEM 3 44 #define AT91_US_USMODE_ISO7816_T0 4 45 #define AT91_US_USMODE_ISO7816_T1 6 46 #define AT91_US_USMODE_IRDA 8 47 #define AT91_US_USCLKS (3 << 4) /* Clock Selection */ 48 #define AT91_US_USCLKS_MCK (0 << 4) 49 #define AT91_US_USCLKS_MCK_DIV8 (1 << 4) 50 #define AT91_US_USCLKS_SCK (3 << 4) 51 #define AT91_US_CHRL (3 << 6) /* Character Length */ 52 #define AT91_US_CHRL_5 (0 << 6) 53 #define AT91_US_CHRL_6 (1 << 6) 54 #define AT91_US_CHRL_7 (2 << 6) 55 #define AT91_US_CHRL_8 (3 << 6) 56 #define AT91_US_SYNC (1 << 8) /* Synchronous Mode Select */ 57 #define AT91_US_PAR (7 << 9) /* Parity Type */ 58 #define AT91_US_PAR_EVEN (0 << 9) 59 #define AT91_US_PAR_ODD (1 << 9) 60 #define AT91_US_PAR_SPACE (2 << 9) 61 #define AT91_US_PAR_MARK (3 << 9) 62 #define AT91_US_PAR_NONE (4 << 9) 63 #define AT91_US_PAR_MULTI_DROP (6 << 9) 64 #define AT91_US_NBSTOP (3 << 12) /* Number of Stop Bits */ 65 #define AT91_US_NBSTOP_1 (0 << 12) 66 #define AT91_US_NBSTOP_1_5 (1 << 12) 67 #define AT91_US_NBSTOP_2 (2 << 12) 68 #define AT91_US_CHMODE (3 << 14) /* Channel Mode */ 69 #define AT91_US_CHMODE_NORMAL (0 << 14) 70 #define AT91_US_CHMODE_ECHO (1 << 14) 71 #define AT91_US_CHMODE_LOC_LOOP (2 << 14) 72 #define AT91_US_CHMODE_REM_LOOP (3 << 14) 73 #define AT91_US_MSBF (1 << 16) /* Bit Order */ 74 #define AT91_US_MODE9 (1 << 17) /* 9-bit Character Length */ 75 #define AT91_US_CLKO (1 << 18) /* Clock Output Select */ 76 #define AT91_US_OVER (1 << 19) /* Oversampling Mode */ 77 #define AT91_US_INACK (1 << 20) /* Inhibit Non Acknowledge */ 78 #define AT91_US_DSNACK (1 << 21) /* Disable Successive NACK */ 79 #define AT91_US_MAX_ITER (7 << 24) /* Max Iterations */ 80 #define AT91_US_FILTER (1 << 28) /* Infrared Receive Line Filter */ 81 82 #define AT91_US_IER 0x08 /* Interrupt Enable Register */ 83 #define AT91_US_RXRDY (1 << 0) /* Receiver Ready */ 84 #define AT91_US_TXRDY (1 << 1) /* Transmitter Ready */ 85 #define AT91_US_RXBRK (1 << 2) /* Break Received / End of Break */ 86 #define AT91_US_ENDRX (1 << 3) /* End of Receiver Transfer */ 87 #define AT91_US_ENDTX (1 << 4) /* End of Transmitter Transfer */ 88 #define AT91_US_OVRE (1 << 5) /* Overrun Error */ 89 #define AT91_US_FRAME (1 << 6) /* Framing Error */ 90 #define AT91_US_PARE (1 << 7) /* Parity Error */ 91 #define AT91_US_TIMEOUT (1 << 8) /* Receiver Time-out */ 92 #define AT91_US_TXEMPTY (1 << 9) /* Transmitter Empty */ 93 #define AT91_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */ 94 #define AT91_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */ 95 #define AT91_US_RXBUFF (1 << 12) /* Reception Buffer Full */ 96 #define AT91_US_NACK (1 << 13) /* Non Acknowledge */ 97 #define AT91_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */ 98 #define AT91_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */ 99 #define AT91_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */ 100 #define AT91_US_CTSIC (1 << 19) /* Clear to Send Input Change */ 101 #define AT91_US_RI (1 << 20) /* RI */ 102 #define AT91_US_DSR (1 << 21) /* DSR */ 103 #define AT91_US_DCD (1 << 22) /* DCD */ 104 #define AT91_US_CTS (1 << 23) /* CTS */ 105 106 #define AT91_US_IDR 0x0c /* Interrupt Disable Register */ 107 #define AT91_US_IMR 0x10 /* Interrupt Mask Register */ 108 #define AT91_US_CSR 0x14 /* Channel Status Register */ 109 #define AT91_US_RHR 0x18 /* Receiver Holding Register */ 110 #define AT91_US_THR 0x1c /* Transmitter Holding Register */ 111 #define AT91_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */ 112 113 #define AT91_US_BRGR 0x20 /* Baud Rate Generator Register */ 114 #define AT91_US_CD (0xffff << 0) /* Clock Divider */ 115 116 #define AT91_US_RTOR 0x24 /* Receiver Time-out Register */ 117 #define AT91_US_TO (0xffff << 0) /* Time-out Value */ 118 119 #define AT91_US_TTGR 0x28 /* Transmitter Timeguard Register */ 120 #define AT91_US_TG (0xff << 0) /* Timeguard Value */ 121 122 #define AT91_US_FIDI 0x40 /* FI DI Ratio Register */ 123 #define AT91_US_NER 0x44 /* Number of Errors Register */ 124 #define AT91_US_IF 0x4c /* IrDA Filter Register */ 125 126 #ifdef __cplusplus 127 } 128 #endif 129 130 #endif 131 132