1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: audmux_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for audmux module.
audmux_iomux_config(void)34 void audmux_iomux_config(void)
35 {
36 // Config audmux.AUD5_RXD to pad DISP0_DATA19(U23)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_WR(0x00000003);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR(0x0001B0B0);
39 // HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_WR(0x00000000);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19(0x020E00DC)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
47 // Select iomux modes to be used for pad.
48 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA19
49 // ALT1 (1) - Select instance: lcd signal: LCD_DATA19
50 // ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SCLK
51 // ALT3 (3) - Select instance: audmux signal: AUD5_RXD
52 // ALT4 (4) - Select instance: audmux signal: AUD4_RXC
53 // ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO13
54 // ALT7 (7) - Select instance: eim signal: EIM_CS3
55 HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_WR(
56 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION_V(DISABLED) |
57 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE_V(ALT3));
58 // Pad Control Register:
59 // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19(0x020E03F0)
60 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
61 // DISABLED (0) - CMOS input
62 // ENABLED (1) - Schmitt trigger input
63 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
64 // 100K_OHM_PD (0) - 100K Ohm Pull Down
65 // 47K_OHM_PU (1) - 47K Ohm Pull Up
66 // 100K_OHM_PU (2) - 100K Ohm Pull Up
67 // 22K_OHM_PU (3) - 22K Ohm Pull Up
68 // PUE [13] - Pull / Keep Select Field Reset: PULL
69 // KEEP (0) - Keeper Enabled
70 // PULL (1) - Pull Enabled
71 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
72 // DISABLED (0) - Pull/Keeper Disabled
73 // ENABLED (1) - Pull/Keeper Enabled
74 // ODE [11] - Open Drain Enable Field Reset: DISABLED
75 // Enables open drain of the pin.
76 // DISABLED (0) - Output is CMOS.
77 // ENABLED (1) - Output is Open Drain.
78 // SPEED [7:6] - Speed Field Reset: 100MHZ
79 // RESERVED0 (0) - Reserved
80 // 50MHZ (1) - Low (50 MHz)
81 // 100MHZ (2) - Medium (100 MHz)
82 // 200MHZ (3) - Maximum (200 MHz)
83 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
84 // HIZ (0) - HI-Z
85 // 240_OHM (1) - 240 Ohm
86 // 120_OHM (2) - 120 Ohm
87 // 80_OHM (3) - 80 Ohm
88 // 60_OHM (4) - 60 Ohm
89 // 48_OHM (5) - 48 Ohm
90 // 40_OHM (6) - 40 Ohm
91 // 34_OHM (7) - 34 Ohm
92 // SRE [0] - Slew Rate Field Reset: SLOW
93 // Slew rate control.
94 // SLOW (0) - Slow Slew Rate
95 // FAST (1) - Fast Slew Rate
96 HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR(
97 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS_V(ENABLED) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS_V(100K_OHM_PU) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE_V(PULL) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE_V(ENABLED) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE_V(DISABLED) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED_V(100MHZ) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE_V(40_OHM) |
104 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE_V(SLOW));
105 // Pad DISP0_DATA19 is involved in Daisy Chain.
106 // Input Select Register:
107 // IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT(0x020E07B0)
108 // DAISY [0] - MUX Mode Select Field Reset: DISP0_DATA19_ALT3
109 // Selecting Pads Involved in Daisy Chain.
110 // DISP0_DATA19_ALT3 (0) - Select signal audmux AUD5_RXD as input from pad DISP0_DATA19(ALT3).
111 // KEY_ROW1_ALT2 (1) - Select signal audmux AUD5_RXD as input from pad KEY_ROW1(ALT2).
112 HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_WR(
113 BF_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY_V(DISP0_DATA19_ALT3));
114
115 // Config audmux.AUD5_TXC to pad DISP0_DATA16(T21)
116 // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR(0x00000003);
117 // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR(0x0001B0B0);
118 // HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_WR(0x00000000);
119 // Mux Register:
120 // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16(0x020E00D0)
121 // SION [4] - Software Input On Field Reset: DISABLED
122 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
123 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
124 // ENABLED (1) - Force input path of pad.
125 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
126 // Select iomux modes to be used for pad.
127 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA16
128 // ALT1 (1) - Select instance: lcd signal: LCD_DATA16
129 // ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_MOSI
130 // ALT3 (3) - Select instance: audmux signal: AUD5_TXC
131 // ALT4 (4) - Select instance: sdma signal: SDMA_EXT_EVENT0
132 // ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO10
133 HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR(
134 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION_V(DISABLED) |
135 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE_V(ALT3));
136 // Pad Control Register:
137 // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16(0x020E03E4)
138 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
139 // DISABLED (0) - CMOS input
140 // ENABLED (1) - Schmitt trigger input
141 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
142 // 100K_OHM_PD (0) - 100K Ohm Pull Down
143 // 47K_OHM_PU (1) - 47K Ohm Pull Up
144 // 100K_OHM_PU (2) - 100K Ohm Pull Up
145 // 22K_OHM_PU (3) - 22K Ohm Pull Up
146 // PUE [13] - Pull / Keep Select Field Reset: PULL
147 // KEEP (0) - Keeper Enabled
148 // PULL (1) - Pull Enabled
149 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
150 // DISABLED (0) - Pull/Keeper Disabled
151 // ENABLED (1) - Pull/Keeper Enabled
152 // ODE [11] - Open Drain Enable Field Reset: DISABLED
153 // Enables open drain of the pin.
154 // DISABLED (0) - Output is CMOS.
155 // ENABLED (1) - Output is Open Drain.
156 // SPEED [7:6] - Speed Field Reset: 100MHZ
157 // RESERVED0 (0) - Reserved
158 // 50MHZ (1) - Low (50 MHz)
159 // 100MHZ (2) - Medium (100 MHz)
160 // 200MHZ (3) - Maximum (200 MHz)
161 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
162 // HIZ (0) - HI-Z
163 // 240_OHM (1) - 240 Ohm
164 // 120_OHM (2) - 120 Ohm
165 // 80_OHM (3) - 80 Ohm
166 // 60_OHM (4) - 60 Ohm
167 // 48_OHM (5) - 48 Ohm
168 // 40_OHM (6) - 40 Ohm
169 // 34_OHM (7) - 34 Ohm
170 // SRE [0] - Slew Rate Field Reset: SLOW
171 // Slew rate control.
172 // SLOW (0) - Slow Slew Rate
173 // FAST (1) - Fast Slew Rate
174 HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR(
175 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS_V(ENABLED) |
176 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS_V(100K_OHM_PU) |
177 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE_V(PULL) |
178 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE_V(ENABLED) |
179 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE_V(DISABLED) |
180 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED_V(100MHZ) |
181 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE_V(40_OHM) |
182 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE_V(SLOW));
183 // Pad DISP0_DATA16 is involved in Daisy Chain.
184 // Input Select Register:
185 // IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT(0x020E07C0)
186 // DAISY [0] - MUX Mode Select Field Reset: DISP0_DATA16_ALT3
187 // Selecting Pads Involved in Daisy Chain.
188 // DISP0_DATA16_ALT3 (0) - Select signal audmux AUD5_TXC as input from pad DISP0_DATA16(ALT3).
189 // KEY_COL0_ALT2 (1) - Select signal audmux AUD5_TXC as input from pad KEY_COL0(ALT2).
190 HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_WR(
191 BF_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_V(DISP0_DATA16_ALT3));
192
193 // Config audmux.AUD5_TXFS to pad DISP0_DATA18(V25)
194 // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_WR(0x00000003);
195 // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR(0x0001B0B0);
196 // HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_WR(0x00000000);
197 // Mux Register:
198 // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18(0x020E00D8)
199 // SION [4] - Software Input On Field Reset: DISABLED
200 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
201 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
202 // ENABLED (1) - Force input path of pad.
203 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
204 // Select iomux modes to be used for pad.
205 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA18
206 // ALT1 (1) - Select instance: lcd signal: LCD_DATA18
207 // ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SS0
208 // ALT3 (3) - Select instance: audmux signal: AUD5_TXFS
209 // ALT4 (4) - Select instance: audmux signal: AUD4_RXFS
210 // ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO12
211 // ALT7 (7) - Select instance: eim signal: EIM_CS2
212 HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_WR(
213 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION_V(DISABLED) |
214 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE_V(ALT3));
215 // Pad Control Register:
216 // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18(0x020E03EC)
217 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
218 // DISABLED (0) - CMOS input
219 // ENABLED (1) - Schmitt trigger input
220 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
221 // 100K_OHM_PD (0) - 100K Ohm Pull Down
222 // 47K_OHM_PU (1) - 47K Ohm Pull Up
223 // 100K_OHM_PU (2) - 100K Ohm Pull Up
224 // 22K_OHM_PU (3) - 22K Ohm Pull Up
225 // PUE [13] - Pull / Keep Select Field Reset: PULL
226 // KEEP (0) - Keeper Enabled
227 // PULL (1) - Pull Enabled
228 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
229 // DISABLED (0) - Pull/Keeper Disabled
230 // ENABLED (1) - Pull/Keeper Enabled
231 // ODE [11] - Open Drain Enable Field Reset: DISABLED
232 // Enables open drain of the pin.
233 // DISABLED (0) - Output is CMOS.
234 // ENABLED (1) - Output is Open Drain.
235 // SPEED [7:6] - Speed Field Reset: 100MHZ
236 // RESERVED0 (0) - Reserved
237 // 50MHZ (1) - Low (50 MHz)
238 // 100MHZ (2) - Medium (100 MHz)
239 // 200MHZ (3) - Maximum (200 MHz)
240 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
241 // HIZ (0) - HI-Z
242 // 240_OHM (1) - 240 Ohm
243 // 120_OHM (2) - 120 Ohm
244 // 80_OHM (3) - 80 Ohm
245 // 60_OHM (4) - 60 Ohm
246 // 48_OHM (5) - 48 Ohm
247 // 40_OHM (6) - 40 Ohm
248 // 34_OHM (7) - 34 Ohm
249 // SRE [0] - Slew Rate Field Reset: SLOW
250 // Slew rate control.
251 // SLOW (0) - Slow Slew Rate
252 // FAST (1) - Fast Slew Rate
253 HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR(
254 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS_V(ENABLED) |
255 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS_V(100K_OHM_PU) |
256 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE_V(PULL) |
257 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE_V(ENABLED) |
258 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE_V(DISABLED) |
259 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED_V(100MHZ) |
260 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE_V(40_OHM) |
261 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE_V(SLOW));
262 // Pad DISP0_DATA18 is involved in Daisy Chain.
263 // Input Select Register:
264 // IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT(0x020E07C4)
265 // DAISY [0] - MUX Mode Select Field Reset: DISP0_DATA18_ALT3
266 // Selecting Pads Involved in Daisy Chain.
267 // DISP0_DATA18_ALT3 (0) - Select signal audmux AUD5_TXFS as input from pad DISP0_DATA18(ALT3).
268 // KEY_COL1_ALT2 (1) - Select signal audmux AUD5_TXFS as input from pad KEY_COL1(ALT2).
269 HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_WR(
270 BF_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_V(DISP0_DATA18_ALT3));
271
272 // Config audmux.AUD6_RXD to pad DI0_PIN04(P25)
273 // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR(0x00000002);
274 // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR(0x0001B0B0);
275 // Mux Register:
276 // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04(0x020E00AC)
277 // SION [4] - Software Input On Field Reset: DISABLED
278 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
279 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
280 // ENABLED (1) - Force input path of pad.
281 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
282 // Select iomux modes to be used for pad.
283 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN04
284 // ALT1 (1) - Select instance: lcd signal: LCD_BUSY
285 // ALT2 (2) - Select instance: audmux signal: AUD6_RXD
286 // ALT3 (3) - Select instance: usdhc1 signal: SD1_WP
287 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO20
288 // ALT8 (8) - Select instance: lcd signal: LCD_RESET
289 HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR(
290 BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION_V(DISABLED) |
291 BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE_V(ALT2));
292 // Pad Control Register:
293 // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04(0x020E03C0)
294 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
295 // DISABLED (0) - CMOS input
296 // ENABLED (1) - Schmitt trigger input
297 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
298 // 100K_OHM_PD (0) - 100K Ohm Pull Down
299 // 47K_OHM_PU (1) - 47K Ohm Pull Up
300 // 100K_OHM_PU (2) - 100K Ohm Pull Up
301 // 22K_OHM_PU (3) - 22K Ohm Pull Up
302 // PUE [13] - Pull / Keep Select Field Reset: PULL
303 // KEEP (0) - Keeper Enabled
304 // PULL (1) - Pull Enabled
305 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
306 // DISABLED (0) - Pull/Keeper Disabled
307 // ENABLED (1) - Pull/Keeper Enabled
308 // ODE [11] - Open Drain Enable Field Reset: DISABLED
309 // Enables open drain of the pin.
310 // DISABLED (0) - Output is CMOS.
311 // ENABLED (1) - Output is Open Drain.
312 // SPEED [7:6] - Speed Field Reset: 100MHZ
313 // RESERVED0 (0) - Reserved
314 // 50MHZ (1) - Low (50 MHz)
315 // 100MHZ (2) - Medium (100 MHz)
316 // 200MHZ (3) - Maximum (200 MHz)
317 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
318 // HIZ (0) - HI-Z
319 // 240_OHM (1) - 240 Ohm
320 // 120_OHM (2) - 120 Ohm
321 // 80_OHM (3) - 80 Ohm
322 // 60_OHM (4) - 60 Ohm
323 // 48_OHM (5) - 48 Ohm
324 // 40_OHM (6) - 40 Ohm
325 // 34_OHM (7) - 34 Ohm
326 // SRE [0] - Slew Rate Field Reset: SLOW
327 // Slew rate control.
328 // SLOW (0) - Slow Slew Rate
329 // FAST (1) - Fast Slew Rate
330 HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR(
331 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS_V(ENABLED) |
332 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS_V(100K_OHM_PU) |
333 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE_V(PULL) |
334 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE_V(ENABLED) |
335 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE_V(DISABLED) |
336 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED_V(100MHZ) |
337 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE_V(40_OHM) |
338 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE_V(SLOW));
339
340 // Config audmux.AUD6_TXC to pad DI0_PIN15(N21)
341 // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR(0x00000002);
342 // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR(0x0001B0B0);
343 // Mux Register:
344 // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15(0x020E00A0)
345 // SION [4] - Software Input On Field Reset: DISABLED
346 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
347 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
348 // ENABLED (1) - Force input path of pad.
349 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
350 // Select iomux modes to be used for pad.
351 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN15
352 // ALT1 (1) - Select instance: lcd signal: LCD_ENABLE
353 // ALT2 (2) - Select instance: audmux signal: AUD6_TXC
354 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO17
355 // ALT8 (8) - Select instance: lcd signal: LCD_RD_E
356 HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR(
357 BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION_V(DISABLED) |
358 BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE_V(ALT2));
359 // Pad Control Register:
360 // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15(0x020E03B4)
361 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
362 // DISABLED (0) - CMOS input
363 // ENABLED (1) - Schmitt trigger input
364 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
365 // 100K_OHM_PD (0) - 100K Ohm Pull Down
366 // 47K_OHM_PU (1) - 47K Ohm Pull Up
367 // 100K_OHM_PU (2) - 100K Ohm Pull Up
368 // 22K_OHM_PU (3) - 22K Ohm Pull Up
369 // PUE [13] - Pull / Keep Select Field Reset: PULL
370 // KEEP (0) - Keeper Enabled
371 // PULL (1) - Pull Enabled
372 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
373 // DISABLED (0) - Pull/Keeper Disabled
374 // ENABLED (1) - Pull/Keeper Enabled
375 // ODE [11] - Open Drain Enable Field Reset: DISABLED
376 // Enables open drain of the pin.
377 // DISABLED (0) - Output is CMOS.
378 // ENABLED (1) - Output is Open Drain.
379 // SPEED [7:6] - Speed Field Reset: 100MHZ
380 // RESERVED0 (0) - Reserved
381 // 50MHZ (1) - Low (50 MHz)
382 // 100MHZ (2) - Medium (100 MHz)
383 // 200MHZ (3) - Maximum (200 MHz)
384 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
385 // HIZ (0) - HI-Z
386 // 240_OHM (1) - 240 Ohm
387 // 120_OHM (2) - 120 Ohm
388 // 80_OHM (3) - 80 Ohm
389 // 60_OHM (4) - 60 Ohm
390 // 48_OHM (5) - 48 Ohm
391 // 40_OHM (6) - 40 Ohm
392 // 34_OHM (7) - 34 Ohm
393 // SRE [0] - Slew Rate Field Reset: SLOW
394 // Slew rate control.
395 // SLOW (0) - Slow Slew Rate
396 // FAST (1) - Fast Slew Rate
397 HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR(
398 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS_V(ENABLED) |
399 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS_V(100K_OHM_PU) |
400 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE_V(PULL) |
401 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE_V(ENABLED) |
402 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE_V(DISABLED) |
403 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED_V(100MHZ) |
404 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE_V(40_OHM) |
405 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE_V(SLOW));
406
407 // Config audmux.AUD6_TXD to pad DI0_PIN02(N25)
408 // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR(0x00000002);
409 // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR(0x0001B0B0);
410 // Mux Register:
411 // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02(0x020E00A4)
412 // SION [4] - Software Input On Field Reset: DISABLED
413 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
414 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
415 // ENABLED (1) - Force input path of pad.
416 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
417 // Select iomux modes to be used for pad.
418 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN02
419 // ALT1 (1) - Select instance: lcd signal: LCD_HSYNC
420 // ALT2 (2) - Select instance: audmux signal: AUD6_TXD
421 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO18
422 // ALT8 (8) - Select instance: lcd signal: LCD_RS
423 HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR(
424 BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION_V(DISABLED) |
425 BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE_V(ALT2));
426 // Pad Control Register:
427 // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02(0x020E03B8)
428 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
429 // DISABLED (0) - CMOS input
430 // ENABLED (1) - Schmitt trigger input
431 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
432 // 100K_OHM_PD (0) - 100K Ohm Pull Down
433 // 47K_OHM_PU (1) - 47K Ohm Pull Up
434 // 100K_OHM_PU (2) - 100K Ohm Pull Up
435 // 22K_OHM_PU (3) - 22K Ohm Pull Up
436 // PUE [13] - Pull / Keep Select Field Reset: PULL
437 // KEEP (0) - Keeper Enabled
438 // PULL (1) - Pull Enabled
439 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
440 // DISABLED (0) - Pull/Keeper Disabled
441 // ENABLED (1) - Pull/Keeper Enabled
442 // ODE [11] - Open Drain Enable Field Reset: DISABLED
443 // Enables open drain of the pin.
444 // DISABLED (0) - Output is CMOS.
445 // ENABLED (1) - Output is Open Drain.
446 // SPEED [7:6] - Speed Field Reset: 100MHZ
447 // RESERVED0 (0) - Reserved
448 // 50MHZ (1) - Low (50 MHz)
449 // 100MHZ (2) - Medium (100 MHz)
450 // 200MHZ (3) - Maximum (200 MHz)
451 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
452 // HIZ (0) - HI-Z
453 // 240_OHM (1) - 240 Ohm
454 // 120_OHM (2) - 120 Ohm
455 // 80_OHM (3) - 80 Ohm
456 // 60_OHM (4) - 60 Ohm
457 // 48_OHM (5) - 48 Ohm
458 // 40_OHM (6) - 40 Ohm
459 // 34_OHM (7) - 34 Ohm
460 // SRE [0] - Slew Rate Field Reset: SLOW
461 // Slew rate control.
462 // SLOW (0) - Slow Slew Rate
463 // FAST (1) - Fast Slew Rate
464 HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR(
465 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS_V(ENABLED) |
466 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS_V(100K_OHM_PU) |
467 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE_V(PULL) |
468 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE_V(ENABLED) |
469 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE_V(DISABLED) |
470 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED_V(100MHZ) |
471 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE_V(40_OHM) |
472 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE_V(SLOW));
473
474 // Config audmux.AUD6_TXFS to pad DI0_PIN03(N20)
475 // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR(0x00000002);
476 // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR(0x0001B0B0);
477 // Mux Register:
478 // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03(0x020E00A8)
479 // SION [4] - Software Input On Field Reset: DISABLED
480 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
481 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
482 // ENABLED (1) - Force input path of pad.
483 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
484 // Select iomux modes to be used for pad.
485 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN03
486 // ALT1 (1) - Select instance: lcd signal: LCD_VSYNC
487 // ALT2 (2) - Select instance: audmux signal: AUD6_TXFS
488 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO19
489 // ALT8 (8) - Select instance: lcd signal: LCD_CS
490 HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR(
491 BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION_V(DISABLED) |
492 BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE_V(ALT2));
493 // Pad Control Register:
494 // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03(0x020E03BC)
495 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
496 // DISABLED (0) - CMOS input
497 // ENABLED (1) - Schmitt trigger input
498 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
499 // 100K_OHM_PD (0) - 100K Ohm Pull Down
500 // 47K_OHM_PU (1) - 47K Ohm Pull Up
501 // 100K_OHM_PU (2) - 100K Ohm Pull Up
502 // 22K_OHM_PU (3) - 22K Ohm Pull Up
503 // PUE [13] - Pull / Keep Select Field Reset: PULL
504 // KEEP (0) - Keeper Enabled
505 // PULL (1) - Pull Enabled
506 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
507 // DISABLED (0) - Pull/Keeper Disabled
508 // ENABLED (1) - Pull/Keeper Enabled
509 // ODE [11] - Open Drain Enable Field Reset: DISABLED
510 // Enables open drain of the pin.
511 // DISABLED (0) - Output is CMOS.
512 // ENABLED (1) - Output is Open Drain.
513 // SPEED [7:6] - Speed Field Reset: 100MHZ
514 // RESERVED0 (0) - Reserved
515 // 50MHZ (1) - Low (50 MHz)
516 // 100MHZ (2) - Medium (100 MHz)
517 // 200MHZ (3) - Maximum (200 MHz)
518 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
519 // HIZ (0) - HI-Z
520 // 240_OHM (1) - 240 Ohm
521 // 120_OHM (2) - 120 Ohm
522 // 80_OHM (3) - 80 Ohm
523 // 60_OHM (4) - 60 Ohm
524 // 48_OHM (5) - 48 Ohm
525 // 40_OHM (6) - 40 Ohm
526 // 34_OHM (7) - 34 Ohm
527 // SRE [0] - Slew Rate Field Reset: SLOW
528 // Slew rate control.
529 // SLOW (0) - Slow Slew Rate
530 // FAST (1) - Fast Slew Rate
531 HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR(
532 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS_V(ENABLED) |
533 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS_V(100K_OHM_PU) |
534 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE_V(PULL) |
535 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE_V(ENABLED) |
536 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE_V(DISABLED) |
537 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED_V(100MHZ) |
538 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE_V(40_OHM) |
539 BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE_V(SLOW));
540 }
541