1 #ifndef __BL602_COMMON_H__
2 #define __BL602_COMMON_H__
3
4 #include "bl602.h"
5 #include "bflb_core.h"
6
7 /**
8 * @brief Memory access macro
9 */
10 #define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr)))
11 #define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val))
12 #define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr)))
13 #define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val))
14 #define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr)))
15 #define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val))
16 #define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
17
18 #define BL_WRWD_TO_BYTEP(p, val) \
19 { \
20 p[0] = val & 0xff; \
21 p[1] = (val >> 8) & 0xff; \
22 p[2] = (val >> 16) & 0xff; \
23 p[3] = (val >> 24) & 0xff; \
24 }
25 /**
26 * @brief Register access macro
27 */
28 #define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET)
29 #define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val)
30 #define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET)
31 #define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val)
32 #define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS))
33 #define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK)
34 #define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS)
35 #define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
36 #define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0)
37 #define BL_DRV_DUMMY \
38 { \
39 __ASM volatile("nop"); \
40 __ASM volatile("nop"); \
41 __ASM volatile("nop"); \
42 __ASM volatile("nop"); \
43 }
44
45 /** @defgroup COMMON_Public_Types
46 * @{
47 */
48 #ifdef BIT
49 #undef BIT
50 #define BIT(n) (1UL << (n))
51 #else
52 #define BIT(n) (1UL << (n))
53 #endif
54
55 /**
56 * @brief Null Type definition
57 */
58 #ifndef NULL
59 #define NULL 0
60 #endif
61
62 /**
63 * @brief Error type definition
64 */
65 typedef enum {
66 SUCCESS = 0,
67 ERROR = 1,
68 TIMEOUT = 2,
69 INVALID = 3, /* invalid arguments */
70 NORESC = 4 /* no resource or resource temperary unavailable */
71 } BL_Err_Type;
72
73 /**
74 * @brief Functional type definition
75 */
76 typedef enum {
77 DISABLE = 0,
78 ENABLE = 1,
79 } BL_Fun_Type;
80
81 /**
82 * @brief Status type definition
83 */
84 typedef enum {
85 RESET = 0,
86 SET = 1,
87 } BL_Sts_Type;
88
89 /**
90 * @brief Mask type definition
91 */
92 typedef enum {
93 UNMASK = 0,
94 MASK = 1
95 } BL_Mask_Type;
96
97 /**
98 * @brief Logical status Type definition
99 */
100 typedef enum {
101 LOGIC_LO = 0,
102 LOGIC_HI = !LOGIC_LO
103 } LogicalStatus;
104
105 /**
106 * @brief Active status Type definition
107 */
108 typedef enum {
109 DEACTIVE = 0,
110 ACTIVE = !DEACTIVE
111 } ActiveStatus;
112
113 /**
114 * @brief Interrupt callback function type
115 */
116 typedef void(intCallback_Type)(void);
117 typedef void (*pFunc)(void);
118
119 #ifdef DEBUG
120 void check_failed(uint8_t *file, uint32_t line);
121 #define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
122 #else
123 #define CHECK_PARAM(expr) ((void)0)
124 #endif /* DEBUG */
125
126 #ifndef __NOP
127 #define __NOP() __ASM volatile("nop") /* This implementation generates debug information */
128 #endif
129 #ifndef __WFI
130 #define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */
131 #endif
132 #ifndef __WFE
133 #define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */
134 #endif
135 #ifndef __SEV
136 #define __SEV() __ASM volatile("sev") /* This implementation generates debug information */
137 #endif
138 #ifndef __set_MSP
139 #define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp))
140 #endif
141
__REV(uint32_t value)142 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
143 {
144 //return __builtin_bswap32(value);
145 uint32_t res = 0;
146
147 res = (value << 24) | (value >> 24);
148 res &= 0xFF0000FF; /* only for sure */
149 res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000);
150
151 return res;
152 }
153
__REV16(uint32_t value)154 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
155 {
156 return __builtin_bswap16(value);
157 }
158
159 /**
160 \brief Enable IRQ Interrupts
161 \details Enables IRQ interrupts by setting the IE-bit in the PSR.
162 Can only be executed in Privileged modes.
163 */
__enable_irq(void)164 __ALWAYS_STATIC_INLINE void __enable_irq(void)
165 {
166 __ASM volatile("csrs mstatus, 8");
167 }
168
169 /**
170 \brief Disable IRQ Interrupts
171 \details Disables IRQ interrupts by clearing the IE-bit in the PSR.
172 Can only be executed in Privileged modes.
173 */
__disable_irq(void)174 __ALWAYS_STATIC_INLINE void __disable_irq(void)
175 {
176 __ASM volatile("csrc mstatus, 8");
177 }
178
179 /** @defgroup COMMON_Public_Constants
180 * @{
181 */
182
183 /** @defgroup DRIVER_INT_PERIPH
184 * @{
185 */
186 #define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)
187
188 /*@} end of group DRIVER_INT_PERIPH */
189
190 /** @defgroup DRIVER_INT_MASK
191 * @{
192 */
193 #define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
194
195 /*@} end of group COMMON_Public_Constants */
196
197 /*@} end of group DRIVER_Public_Macro */
198 #define BL602_MemCpy arch_memcpy
199 #define BL602_MemSet arch_memset
200 #define BL602_MemCmp arch_memcmp
201 #define BL602_MemCpy4 arch_memcpy4
202 #define BL602_MemCpy_Fast arch_memcpy_fast
203 #define BL602_MemSet4 arch_memset4
204
205 #define BL602_Delay_US arch_delay_us
206 #define BL602_Delay_MS arch_delay_ms
207
208 #define BFLB_Soft_CRC32 bflb_soft_crc32
209 #define CPU_Interrupt_Enable(irq)
210 #define CPU_Interrupt_Disable(irq)
211 #define Interrupt_Handler_Register(irq, callback)
212
213 void BL602_Delay_US(uint32_t cnt);
214 void BL602_Delay_MS(uint32_t cnt);
215 #endif
216