1 /** 2 ****************************************************************************** 3 * @file bl602_glb.h 4 * @version V1.0 5 * @date 6 * @brief This file is the standard driver header file 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __BL602_GLB_H__ 37 #define __BL602_GLB_H__ 38 39 #include "glb_reg.h" 40 #include "pds_reg.h" 41 #include "bl602_gpio.h" 42 #include "bl602_l1c.h" 43 #include "bl602_hbn.h" 44 #include "bl602_aon.h" 45 #include "bl602_pds.h" 46 #include "bl602_common.h" 47 #include "bflb_sf_ctrl.h" 48 #include "bflb_sf_cfg.h" 49 50 /** @addtogroup BL602_Peripheral_Driver 51 * @{ 52 */ 53 54 /** @addtogroup GLB 55 * @{ 56 */ 57 58 /** @defgroup GLB_Public_Types 59 * @{ 60 */ 61 62 /** 63 * @brief GLB root clock type definition 64 */ 65 typedef enum { 66 GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */ 67 GLB_ROOT_CLK_XTAL, /*!< root clock select XTAL */ 68 GLB_ROOT_CLK_PLL, /*!< root clock select PLL others */ 69 } GLB_ROOT_CLK_Type; 70 71 /** 72 * @brief GLB system clock type definition 73 */ 74 typedef enum { 75 GLB_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */ 76 GLB_SYS_CLK_XTAL, /*!< use XTAL as system clock */ 77 GLB_SYS_CLK_PLL48M, /*!< use PLL output 48M as system clock */ 78 GLB_SYS_CLK_PLL120M, /*!< use PLL output 120M as system clock */ 79 GLB_SYS_CLK_PLL160M, /*!< use PLL output 160M as system clock */ 80 GLB_SYS_CLK_PLL192M, /*!< use PLL output 192M as system clock */ 81 } GLB_SYS_CLK_Type; 82 83 /** 84 * @brief GLB DMA clock ID type definition 85 */ 86 typedef enum { 87 GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */ 88 GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */ 89 GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */ 90 GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */ 91 } GLB_DMA_CLK_ID_Type; 92 93 /** 94 * @brief GLB clock source type definition 95 */ 96 typedef enum { 97 GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */ 98 } GLB_IR_CLK_SRC_Type; 99 100 /** 101 * @brief GLB flash clock type definition 102 */ 103 typedef enum { 104 GLB_SFLASH_CLK_120M, /*!< Select 120M as flash clock */ 105 GLB_SFLASH_CLK_XTAL, /*!< Select XTAL as flash clock */ 106 GLB_SFLASH_CLK_48M, /*!< Select 48M as flash clock */ 107 GLB_SFLASH_CLK_80M, /*!< Select 80M as flash clock */ 108 GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */ 109 GLB_SFLASH_CLK_96M, /*!< Select 96M as flash clock */ 110 } GLB_SFLASH_CLK_Type; 111 112 /** 113 * @brief GLB SPI pad action type definition 114 */ 115 typedef enum { 116 GLB_SPI_PAD_ACT_AS_SLAVE, /*!< SPI pad act as slave */ 117 GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */ 118 } GLB_SPI_PAD_ACT_AS_Type; 119 120 /** 121 * @brief GLB PKA clock type definition 122 */ 123 typedef enum { 124 GLB_PKA_CLK_HCLK, /*!< Select HCLK as PKA clock */ 125 GLB_PKA_CLK_PLL120M, /*!< Select PLL 120M as PKA clock */ 126 } GLB_PKA_CLK_Type; 127 128 /** 129 * @brief BMX arb mode type definition 130 */ 131 typedef enum { 132 BMX_ARB_FIX, /*!< 0->fix */ 133 BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ 134 BMX_ARB_RANDOM, /*!< 3->random */ 135 } BMX_ARB_Type; 136 137 /** 138 * @brief BMX configuration structure type definition 139 */ 140 typedef struct 141 { 142 uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ 143 BL_Fun_Type errEn; /*!< Bus error response enable */ 144 BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ 145 } BMX_Cfg_Type; 146 147 /** 148 * @brief BMX bus err type definition 149 */ 150 typedef enum { 151 BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ 152 BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ 153 } BMX_BUS_ERR_Type; 154 155 /** 156 * @brief BMX bus err interrupt type definition 157 */ 158 typedef enum { 159 BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */ 160 BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */ 161 } BMX_ERR_INT_Type; 162 163 /** 164 * @brief BMX time out interrupt type definition 165 */ 166 typedef enum { 167 BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */ 168 BMX_TO_INT_ALL, /*!< BMX timeout interrupt max num */ 169 } BMX_TO_INT_Type; 170 171 /** 172 * @brief GLB EM type definition 173 */ 174 typedef enum { 175 GLB_EM_0KB = 0x0, /*!< 0x0 --> 0KB */ 176 GLB_EM_8KB = 0x3, /*!< 0x3 --> 8KB */ 177 GLB_EM_16KB = 0xF, /*!< 0xF --> 16KB */ 178 } GLB_EM_Type; 179 180 /** 181 * @brief GLB RTC clock type definition 182 */ 183 typedef enum { 184 GLB_MTIMER_CLK_BCLK, /*!< BUS clock */ 185 GLB_MTIMER_CLK_32K, /*!< 32KHz */ 186 } GLB_MTIMER_CLK_Type; 187 188 /** 189 * @brief GLB ADC clock type definition 190 */ 191 typedef enum { 192 GLB_ADC_CLK_96M, /*!< use 96M as ADC clock */ 193 GLB_ADC_CLK_XCLK, /*!< use XCLK as ADC clock */ 194 } GLB_ADC_CLK_Type; 195 196 /** 197 * @brief GLB DAC clock type definition 198 */ 199 typedef enum { 200 GLB_DAC_CLK_32M, /*!< use 32M as DAC clock */ 201 GLB_DAC_CLK_XCLK, /*!< use XCLK as DAC clock */ 202 } GLB_DAC_CLK_Type; 203 204 /** 205 * @brief GLB DIG clock source select type definition 206 */ 207 typedef enum { 208 GLB_DIG_CLK_PLL_32M, /*!< select PLL 32M as DIG clock source */ 209 GLB_DIG_CLK_XCLK, /*!< select XCLK as DIG clock source */ 210 } GLB_DIG_CLK_Type; 211 212 /** 213 * @brief GLB 512K clock out select type definition 214 */ 215 typedef enum { 216 GLB_512K_CLK_OUT_512K, /*!< select 512K clock out */ 217 GLB_512K_CLK_OUT_256K, /*!< select 256K clock out */ 218 GLB_512K_CLK_OUT_128K, /*!< select 128K clock out */ 219 } GLB_512K_CLK_OUT_Type; 220 221 /** 222 * @brief GLB BT bandwidth type definition 223 */ 224 typedef enum { 225 GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */ 226 GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */ 227 } GLB_BT_BANDWIDTH_Type; 228 229 /** 230 * @brief GLB UART signal type definition 231 */ 232 typedef enum { 233 GLB_UART_SIG_0, /*!< UART signal 0 */ 234 GLB_UART_SIG_1, /*!< UART signal 1 */ 235 GLB_UART_SIG_2, /*!< UART signal 2 */ 236 GLB_UART_SIG_3, /*!< UART signal 3 */ 237 GLB_UART_SIG_4, /*!< UART signal 4 */ 238 GLB_UART_SIG_5, /*!< UART signal 5 */ 239 GLB_UART_SIG_6, /*!< UART signal 6 */ 240 GLB_UART_SIG_7, /*!< UART signal 7 */ 241 } GLB_UART_SIG_Type; 242 243 /** 244 * @brief GLB UART signal function type definition 245 */ 246 typedef enum { 247 GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */ 248 GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */ 249 GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */ 250 GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */ 251 GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */ 252 GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */ 253 GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */ 254 GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */ 255 } GLB_UART_SIG_FUN_Type; 256 257 /** 258 * @brief GLB GPIO real mode type definition 259 */ 260 typedef enum { 261 GLB_GPIO_REAL_MODE_REG, /*!< GPIO real function is reg_gpio_x_func_sel */ 262 GLB_GPIO_REAL_MODE_SDIO = 0x1, /*!< GPIO real function is SDIO */ 263 GLB_GPIO_REAL_MODE_RF = 0xC, /*!< GPIO real function is RF */ 264 GLB_GPIO_REAL_MODE_JTAG = 0xE, /*!< GPIO real function is JTAG */ 265 GLB_GPIO_REAL_MODE_CCI = 0xF, /*!< GPIO real function is CCI */ 266 } GLB_GPIO_REAL_MODE_Type; 267 268 /** 269 * @brief GLB GPIO interrupt trigger mode type definition 270 */ 271 typedef enum { 272 GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */ 273 GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */ 274 GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */ 275 GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */ 276 } GLB_GPIO_INT_TRIG_Type; 277 278 /** 279 * @brief GLB GPIO interrupt control mode type definition 280 */ 281 typedef enum { 282 GLB_GPIO_INT_CONTROL_SYNC, /*!< GPIO interrupt sync mode */ 283 GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */ 284 } GLB_GPIO_INT_CONTROL_Type; 285 286 /** 287 * @brief PLL XTAL type definition 288 */ 289 typedef enum { 290 GLB_PLL_XTAL_NONE, /*!< XTAL is none */ 291 GLB_PLL_XTAL_24M, /*!< XTAL is 24M */ 292 GLB_PLL_XTAL_32M, /*!< XTAL is 32M */ 293 GLB_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */ 294 GLB_PLL_XTAL_40M, /*!< XTAL is 40M */ 295 GLB_PLL_XTAL_26M, /*!< XTAL is 26M */ 296 GLB_PLL_XTAL_RC32M, /*!< XTAL is RC32M */ 297 } GLB_PLL_XTAL_Type; 298 299 /** 300 * @brief PLL output clock type definition 301 */ 302 typedef enum { 303 GLB_PLL_CLK_480M, /*!< PLL output clock:480M */ 304 GLB_PLL_CLK_240M, /*!< PLL output clock:240M */ 305 GLB_PLL_CLK_192M, /*!< PLL output clock:192M */ 306 GLB_PLL_CLK_160M, /*!< PLL output clock:160M */ 307 GLB_PLL_CLK_120M, /*!< PLL output clock:120M */ 308 GLB_PLL_CLK_96M, /*!< PLL output clock:96M */ 309 GLB_PLL_CLK_80M, /*!< PLL output clock:80M */ 310 GLB_PLL_CLK_48M, /*!< PLL output clock:48M */ 311 GLB_PLL_CLK_32M, /*!< PLL output clock:32M */ 312 } GLB_PLL_CLK_Type; 313 314 /** 315 * @brief PLL configuration structure type definition 316 */ 317 typedef struct 318 { 319 uint8_t clkpllIcp1u; /*!< int mode:0, frac mode:1 */ 320 uint8_t clkpllIcp5u; /*!< int mode:2, frac mode:0 */ 321 uint8_t clkpllIntFracSw; /*!< 0:int mode, 1:frac mode */ 322 uint8_t clkpllC3; /*!< int:3, frac:2 */ 323 uint8_t clkpllCz; /*!< int:1, frac:2 */ 324 uint8_t clkpllRz; /*!< int:1, frac:5 */ 325 uint8_t clkpllR4; /*!< int:2, frac:2 */ 326 uint8_t clkpllR4Short; /*!< int:1, frac:0 */ 327 uint8_t clkpllRefdivRatio; /*!< ref divider ratio */ 328 uint8_t clkpllPostdiv; /*!< >=8 and should be even number */ 329 uint32_t clkpllSdmin; /*!< sdmin */ 330 uint8_t clkpllSelFbClk; /*!< 0:mod1, 1:mod2, 2:mod3 */ 331 uint8_t clkpllSelSampleClk; /*!< 0:[16,63)mod3, 1:[32:127)mod4, 2:[64,255)mod5 */ 332 } GLB_PLL_Cfg_Type; 333 334 /*@} end of group GLB_Public_Types */ 335 336 /** @defgroup GLB_Public_Constants 337 * @{ 338 */ 339 340 /** @defgroup GLB_ROOT_CLK_TYPE 341 * @{ 342 */ 343 #define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \ 344 ((type) == GLB_ROOT_CLK_XTAL) || \ 345 ((type) == GLB_ROOT_CLK_PLL)) 346 347 /** @defgroup GLB_SYS_CLK_TYPE 348 * @{ 349 */ 350 #define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) || \ 351 ((type) == GLB_SYS_CLK_XTAL) || \ 352 ((type) == GLB_SYS_CLK_PLL48M) || \ 353 ((type) == GLB_SYS_CLK_PLL120M) || \ 354 ((type) == GLB_SYS_CLK_PLL160M) || \ 355 ((type) == GLB_SYS_CLK_PLL192M)) 356 357 /** @defgroup GLB_DMA_CLK_ID_TYPE 358 * @{ 359 */ 360 #define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \ 361 ((type) == GLB_DMA_CLK_DMA0_CH1) || \ 362 ((type) == GLB_DMA_CLK_DMA0_CH2) || \ 363 ((type) == GLB_DMA_CLK_DMA0_CH3)) 364 365 /** @defgroup GLB_IR_CLK_SRC_TYPE 366 * @{ 367 */ 368 #define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK)) 369 370 /** @defgroup GLB_SFLASH_CLK_TYPE 371 * @{ 372 */ 373 #define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_120M) || \ 374 ((type) == GLB_SFLASH_CLK_XTAL) || \ 375 ((type) == GLB_SFLASH_CLK_48M) || \ 376 ((type) == GLB_SFLASH_CLK_80M) || \ 377 ((type) == GLB_SFLASH_CLK_BCLK) || \ 378 ((type) == GLB_SFLASH_CLK_96M)) 379 380 /** @defgroup GLB_SPI_PAD_ACT_AS_TYPE 381 * @{ 382 */ 383 #define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \ 384 ((type) == GLB_SPI_PAD_ACT_AS_MASTER)) 385 386 /** @defgroup GLB_PKA_CLK_TYPE 387 * @{ 388 */ 389 #define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \ 390 ((type) == GLB_PKA_CLK_PLL120M)) 391 392 /** @defgroup BMX_ARB_TYPE 393 * @{ 394 */ 395 #define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) || \ 396 ((type) == BMX_ARB_ROUND_ROBIN) || \ 397 ((type) == BMX_ARB_RANDOM)) 398 399 /** @defgroup BMX_BUS_ERR_TYPE 400 * @{ 401 */ 402 #define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \ 403 ((type) == BMX_BUS_ERR_ADDR_DECODE)) 404 405 /** @defgroup BMX_ERR_INT_TYPE 406 * @{ 407 */ 408 #define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \ 409 ((type) == BMX_ERR_INT_ALL)) 410 411 /** @defgroup BMX_TO_INT_TYPE 412 * @{ 413 */ 414 #define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \ 415 ((type) == BMX_TO_INT_ALL)) 416 417 /** @defgroup GLB_EM_TYPE 418 * @{ 419 */ 420 #define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \ 421 ((type) == GLB_EM_8KB) || \ 422 ((type) == GLB_EM_16KB)) 423 424 /** @defgroup GLB_MTIMER_CLK_TYPE 425 * @{ 426 */ 427 #define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \ 428 ((type) == GLB_MTIMER_CLK_32K)) 429 430 /** @defgroup GLB_ADC_CLK_TYPE 431 * @{ 432 */ 433 #define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_96M) || \ 434 ((type) == GLB_ADC_CLK_XCLK)) 435 436 /** @defgroup GLB_DAC_CLK_TYPE 437 * @{ 438 */ 439 #define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_32M) || \ 440 ((type) == GLB_DAC_CLK_XCLK)) 441 442 /** @defgroup GLB_DIG_CLK_TYPE 443 * @{ 444 */ 445 #define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \ 446 ((type) == GLB_DIG_CLK_XCLK)) 447 448 /** @defgroup GLB_512K_CLK_OUT_TYPE 449 * @{ 450 */ 451 #define IS_GLB_512K_CLK_OUT_TYPE(type) (((type) == GLB_512K_CLK_OUT_512K) || \ 452 ((type) == GLB_512K_CLK_OUT_256K) || \ 453 ((type) == GLB_512K_CLK_OUT_128K)) 454 455 /** @defgroup GLB_BT_BANDWIDTH_TYPE 456 * @{ 457 */ 458 #define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \ 459 ((type) == GLB_BT_BANDWIDTH_2M)) 460 461 /** @defgroup GLB_UART_SIG_TYPE 462 * @{ 463 */ 464 #define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \ 465 ((type) == GLB_UART_SIG_1) || \ 466 ((type) == GLB_UART_SIG_2) || \ 467 ((type) == GLB_UART_SIG_3) || \ 468 ((type) == GLB_UART_SIG_4) || \ 469 ((type) == GLB_UART_SIG_5) || \ 470 ((type) == GLB_UART_SIG_6) || \ 471 ((type) == GLB_UART_SIG_7)) 472 473 /** @defgroup GLB_UART_SIG_FUN_TYPE 474 * @{ 475 */ 476 #define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \ 477 ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \ 478 ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \ 479 ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \ 480 ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \ 481 ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \ 482 ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \ 483 ((type) == GLB_UART_SIG_FUN_UART1_RXD)) 484 485 /** @defgroup GLB_GPIO_REAL_MODE_TYPE 486 * @{ 487 */ 488 #define IS_GLB_GPIO_REAL_MODE_TYPE(type) (((type) == GLB_GPIO_REAL_MODE_REG) || \ 489 ((type) == GLB_GPIO_REAL_MODE_SDIO) || \ 490 ((type) == GLB_GPIO_REAL_MODE_RF) || \ 491 ((type) == GLB_GPIO_REAL_MODE_JTAG) || \ 492 ((type) == GLB_GPIO_REAL_MODE_CCI)) 493 494 /** @defgroup GLB_GPIO_INT_TRIG_TYPE 495 * @{ 496 */ 497 #define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \ 498 ((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \ 499 ((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \ 500 ((type) == GLB_GPIO_INT_TRIG_POS_LEVEL)) 501 502 /** @defgroup GLB_GPIO_INT_CONTROL_TYPE 503 * @{ 504 */ 505 #define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \ 506 ((type) == GLB_GPIO_INT_CONTROL_ASYNC)) 507 508 /** @defgroup GLB_PLL_XTAL_TYPE 509 * @{ 510 */ 511 #define IS_GLB_PLL_XTAL_TYPE(type) (((type) == GLB_PLL_XTAL_NONE) || \ 512 ((type) == GLB_PLL_XTAL_24M) || \ 513 ((type) == GLB_PLL_XTAL_32M) || \ 514 ((type) == GLB_PLL_XTAL_38P4M) || \ 515 ((type) == GLB_PLL_XTAL_40M) || \ 516 ((type) == GLB_PLL_XTAL_26M) || \ 517 ((type) == GLB_PLL_XTAL_RC32M)) 518 519 /** @defgroup GLB_PLL_CLK_TYPE 520 * @{ 521 */ 522 #define IS_GLB_PLL_CLK_TYPE(type) (((type) == GLB_PLL_CLK_480M) || \ 523 ((type) == GLB_PLL_CLK_240M) || \ 524 ((type) == GLB_PLL_CLK_192M) || \ 525 ((type) == GLB_PLL_CLK_160M) || \ 526 ((type) == GLB_PLL_CLK_120M) || \ 527 ((type) == GLB_PLL_CLK_96M) || \ 528 ((type) == GLB_PLL_CLK_80M) || \ 529 ((type) == GLB_PLL_CLK_48M) || \ 530 ((type) == GLB_PLL_CLK_32M)) 531 532 /*@} end of group GLB_Public_Constants */ 533 534 /** @defgroup GLB_Public_Macros 535 * @{ 536 */ 537 #define UART_SIG_SWAP_GPIO0_GPIO7 0x01 /* GPIO0-7 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ 538 #define UART_SIG_SWAP_GPIO8_GPIO15 0x02 /* GPIO8-15 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ 539 #define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ 540 #define UART_SIG_SWAP_NONE 0x00 /* GPIO0-22 uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */ 541 #define JTAG_SIG_SWAP_GPIO0_GPIO3 0x01 /* GPIO0-3 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 542 #define JTAG_SIG_SWAP_GPIO4_GPIO7 0x02 /* GPIO4-7 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 543 #define JTAG_SIG_SWAP_GPIO8_GPIO11 0x04 /* GPIO8-11 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 544 #define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 545 #define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 546 #define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 547 #define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 548 549 /*@} end of group GLB_Public_Macros */ 550 551 /** @defgroup GLB_Public_Functions 552 * @{ 553 */ 554 /*----------*/ 555 #ifndef BFLB_USE_HAL_DRIVER 556 void BMX_ERR_IRQHandler(void); 557 void BMX_TO_IRQHandler(void); 558 void GPIO_INT0_IRQHandler(void); 559 #endif 560 /*----------*/ 561 GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void); 562 BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv); 563 uint8_t GLB_Get_BCLK_Div(void); 564 uint8_t GLB_Get_HCLK_Div(void); 565 BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType); 566 BL_Err_Type GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq); 567 BL_Err_Type System_Core_Clock_Update_From_RC32M(void); 568 /*----------*/ 569 BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable); 570 BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv); 571 BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv); 572 BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk); 573 BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div); 574 BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div); 575 BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div); 576 BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div); 577 BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div); 578 /*----------*/ 579 BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel); 580 BL_Err_Type GLB_SW_System_Reset(void); 581 BL_Err_Type GLB_SW_CPU_Reset(void); 582 BL_Err_Type GLB_SW_POR_Reset(void); 583 BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1); 584 BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1); 585 /*----------*/ 586 BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg); 587 BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void); 588 BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void); 589 BL_Err_Type GLB_BMX_BusErrResponse_Enable(void); 590 BL_Err_Type GLB_BMX_BusErrResponse_Disable(void); 591 BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType); 592 uint32_t GLB_BMX_Get_Err_Addr(void); 593 BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun); 594 BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun); 595 /*----------*/ 596 BL_Err_Type GLB_Set_OCRAM_Idle(void); 597 BL_Err_Type GLB_Set_SRAM_RET(uint32_t value); 598 uint32_t GLB_Get_SRAM_RET(void); 599 BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value); 600 uint32_t GLB_Get_SRAM_SLP(void); 601 BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value); 602 uint32_t GLB_Get_SRAM_PARM(void); 603 /*----------*/ 604 BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType); 605 /*----------*/ 606 BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel); 607 BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel); 608 BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState); 609 BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod); 610 BL_Err_Type GLB_Select_Internal_Flash(void); 611 BL_Err_Type GLB_Select_External_Flash(void); 612 BL_Err_Type GLB_Deswap_Flash_Pin(void); 613 BL_Err_Type GLB_Swap_Flash_Pin(void); 614 /*----------*/ 615 BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div); 616 /*----------*/ 617 BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div); 618 BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div); 619 /*----------*/ 620 BL_Err_Type GLB_Platform_Wakeup_Enable(void); 621 BL_Err_Type GLB_Platform_Wakeup_Disable(void); 622 /*----------*/ 623 BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel); 624 BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div); 625 BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint16_t div); 626 /*----------*/ 627 BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, 628 uint8_t pti, uint8_t channel); 629 /*----------*/ 630 BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun); 631 /*----------*/ 632 BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio); 633 BL_Err_Type GLB_IR_LED_Driver_Enable(void); 634 BL_Err_Type GLB_IR_LED_Driver_Disable(void); 635 BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias); 636 /*----------*/ 637 BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg); 638 BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt); 639 BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin); 640 BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin); 641 BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin); 642 BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin); 643 BL_Err_Type GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin); 644 BL_Err_Type GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin); 645 BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin); 646 uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin); 647 GLB_GPIO_REAL_MODE_Type GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin); 648 BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val); 649 uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin); 650 BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask); 651 BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear); 652 BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin); 653 BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin); 654 BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, 655 GLB_GPIO_INT_TRIG_Type intTrgMod); 656 GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin); 657 BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void); 658 BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun); 659 660 /*@} end of group GLB_Public_Functions */ 661 662 /*@} end of group GLB */ 663 664 /*@} end of group BL602_Peripheral_Driver */ 665 666 #endif /* __BL602_GLB_H__ */ 667