1 /** 2 ****************************************************************************** 3 * @file bl602_hbn.h 4 * @version V1.0 5 * @date 6 * @brief This file is the standard driver header file 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __BL602_HBN_H__ 37 #define __BL602_HBN_H__ 38 39 #include "hbn_reg.h" 40 #include "bl602_aon.h" 41 #include "bflb_sflash.h" 42 #include "bl602_common.h" 43 44 /** @addtogroup BL602_Peripheral_Driver 45 * @{ 46 */ 47 48 /** @addtogroup HBN 49 * @{ 50 */ 51 52 /** @defgroup HBN_Public_Types 53 * @{ 54 */ 55 56 /** 57 * @brief HBN PIR interrupt configuration type definition 58 */ 59 typedef struct 60 { 61 BL_Fun_Type lowIntEn; /*!< Low will trigger interrupt */ 62 BL_Fun_Type highIntEn; /*!< High will trigger interrupt */ 63 } HBN_PIR_INT_CFG_Type; 64 65 /** 66 * @brief HBN PIR low pass filter type definition 67 */ 68 typedef enum { 69 HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */ 70 HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */ 71 } HBN_PIR_LPF_Type; 72 73 /** 74 * @brief HBN PIR high pass filter type definition 75 */ 76 typedef enum { 77 HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */ 78 HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */ 79 HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */ 80 } HBN_PIR_HPF_Type; 81 82 /** 83 * @brief HBN BOR threshold type definition 84 */ 85 typedef enum { 86 HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */ 87 HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */ 88 } HBN_BOR_THRES_Type; 89 90 /** 91 * @brief HBN BOR mode type definition 92 */ 93 typedef enum { 94 HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */ 95 HBN_BOR_MODE_POR_RELEVANT, /*!< POR is relevant to BOR */ 96 } HBN_BOR_MODE_Type; 97 98 /** 99 * @brief HBN 32K clock type definition 100 */ 101 typedef enum { 102 HBN_32K_RC = 0, /*!< HBN use rc 32k */ 103 HBN_32K_XTAL, /*!< HBN use xtal 32k */ 104 HBN_32K_DIG = 3, /*!< HBN use dig 32k */ 105 } HBN_32K_CLK_Type; 106 107 /** 108 * @brief HBN xclk clock type definition 109 */ 110 typedef enum { 111 HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */ 112 HBN_XCLK_CLK_XTAL, /*!< use XTAL as xclk clock */ 113 } HBN_XCLK_CLK_Type; 114 115 /** 116 * @brief HBN root clock type definition 117 */ 118 typedef enum { 119 HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */ 120 HBN_ROOT_CLK_XTAL, /*!< use XTAL as root clock */ 121 HBN_ROOT_CLK_PLL, /*!< use PLL as root clock */ 122 } HBN_ROOT_CLK_Type; 123 124 /** 125 * @brief HBN UART clock type definition 126 */ 127 typedef enum { 128 HBN_UART_CLK_FCLK = 0, /*!< Select FCLK as UART clock */ 129 HBN_UART_CLK_160M, /*!< Select 160M as UART clock */ 130 } HBN_UART_CLK_Type; 131 132 /** 133 * @brief HBN RTC interrupt delay type definition 134 */ 135 typedef enum { 136 HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */ 137 HBN_RTC_INT_DELAY_0T = 1, /*!< HBN RTC interrupt delay 0T */ 138 } HBN_RTC_INT_Delay_Type; 139 140 /** 141 * @brief HBN interrupt type definition 142 */ 143 typedef enum { 144 HBN_INT_GPIO7 = 0, /*!< HBN interrupt type: GPIO7 */ 145 HBN_INT_GPIO8 = 1, /*!< HBN interrupt type: GPIO8 */ 146 HBN_INT_RTC = 16, /*!< HBN interrupt type: RTC */ 147 HBN_INT_PIR = 17, /*!< HBN interrupt type: PIR */ 148 HBN_INT_BOR = 18, /*!< HBN interrupt type: BOR */ 149 HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */ 150 HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */ 151 } HBN_INT_Type; 152 153 /** 154 * @brief HBN acomp interrupt type definition 155 */ 156 typedef enum { 157 HBN_ACOMP_INT_EDGE_POSEDGE = 0, /*!< HBN acomp interrupt edge posedge */ 158 HBN_ACOMP_INT_EDGE_NEGEDGE = 1, /*!< HBN acomp interrupt edge negedge */ 159 } HBN_ACOMP_INT_EDGE_Type; 160 161 /** 162 * @brief HBN GPIO interrupt trigger type definition 163 */ 164 typedef enum { 165 HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: sync falling edge trigger */ 166 HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: sync rising edge trigger */ 167 HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: sync low level trigger */ 168 HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: sync high level trigger */ 169 HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */ 170 HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: async rising edge trigger */ 171 HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: async low level trigger */ 172 HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: async high level trigger */ 173 } HBN_GPIO_INT_Trigger_Type; 174 175 /** 176 * @brief HBN OUT0 interrupt type definition 177 */ 178 typedef enum { 179 HBN_OUT0_INT_GPIO7 = 0, /*!< HBN out 0 interrupt type: GPIO7 */ 180 HBN_OUT0_INT_GPIO8, /*!< HBN out 0 interrupt type: GPIO8 */ 181 HBN_OUT0_INT_RTC, /*!< HBN out 0 interrupt type: RTC */ 182 } HBN_OUT0_INT_Type; 183 184 /** 185 * @brief HBN OUT0 interrupt type definition 186 */ 187 typedef enum { 188 HBN_OUT1_INT_PIR, /*!< HBN out 1 interrupt type: PIR */ 189 HBN_OUT1_INT_BOR, /*!< HBN out 1 interrupt type: BOR */ 190 HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */ 191 HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */ 192 } HBN_OUT1_INT_Type; 193 194 /** 195 * @brief HBN LDO level type definition 196 */ 197 typedef enum { 198 HBN_LDO_LEVEL_0P60V = 0, /*!< HBN LDO voltage 0.60V */ 199 HBN_LDO_LEVEL_0P65V = 1, /*!< HBN LDO voltage 0.65V */ 200 HBN_LDO_LEVEL_0P70V = 2, /*!< HBN LDO voltage 0.70V */ 201 HBN_LDO_LEVEL_0P75V = 3, /*!< HBN LDO voltage 0.75V */ 202 HBN_LDO_LEVEL_0P80V = 4, /*!< HBN LDO voltage 0.80V */ 203 HBN_LDO_LEVEL_0P85V = 5, /*!< HBN LDO voltage 0.85V */ 204 HBN_LDO_LEVEL_0P90V = 6, /*!< HBN LDO voltage 0.90V */ 205 HBN_LDO_LEVEL_0P95V = 7, /*!< HBN LDO voltage 0.95V */ 206 HBN_LDO_LEVEL_1P00V = 8, /*!< HBN LDO voltage 1.00V */ 207 HBN_LDO_LEVEL_1P05V = 9, /*!< HBN LDO voltage 1.05V */ 208 HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */ 209 HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */ 210 HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */ 211 HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */ 212 HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */ 213 HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */ 214 } HBN_LDO_LEVEL_Type; 215 216 /** 217 * @brief HBN level type definition 218 */ 219 typedef enum { 220 HBN_LEVEL_0, /*!< HBN pd_core */ 221 HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */ 222 HBN_LEVEL_2, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ 223 HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ 224 } HBN_LEVEL_Type; 225 226 /** 227 * @brief HBN BOR configuration type definition 228 */ 229 typedef struct 230 { 231 uint8_t enableBor; /*!< Enable BOR or not */ 232 uint8_t enableBorInt; /*!< Enable BOR interrupt or not */ 233 uint8_t borThreshold; /*!< BOR threshold */ 234 uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */ 235 } HBN_BOR_CFG_Type; 236 237 /** 238 * @brief HBN APP configuration type definition 239 */ 240 typedef struct 241 { 242 uint8_t useXtal32k; /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */ 243 uint32_t sleepTime; /*!< HBN sleep time */ 244 uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */ 245 HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */ 246 spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ 247 HBN_LEVEL_Type hbnLevel; /*!< HBN level */ 248 HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ 249 } HBN_APP_CFG_Type; 250 251 /*@} end of group HBN_Public_Types */ 252 253 /** @defgroup HBN_Public_Constants 254 * @{ 255 */ 256 257 /** @defgroup HBN_PIR_LPF_TYPE 258 * @{ 259 */ 260 #define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \ 261 ((type) == HBN_PIR_LPF_DIV2)) 262 263 /** @defgroup HBN_PIR_HPF_TYPE 264 * @{ 265 */ 266 #define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \ 267 ((type) == HBN_PIR_HPF_METHOD1) || \ 268 ((type) == HBN_PIR_HPF_METHOD2)) 269 270 /** @defgroup HBN_BOR_THRES_TYPE 271 * @{ 272 */ 273 #define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \ 274 ((type) == HBN_BOR_THRES_2P4V)) 275 276 /** @defgroup HBN_BOR_MODE_TYPE 277 * @{ 278 */ 279 #define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \ 280 ((type) == HBN_BOR_MODE_POR_RELEVANT)) 281 282 /** @defgroup HBN_32K_CLK_TYPE 283 * @{ 284 */ 285 #define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) || \ 286 ((type) == HBN_32K_XTAL) || \ 287 ((type) == HBN_32K_DIG)) 288 289 /** @defgroup HBN_XCLK_CLK_TYPE 290 * @{ 291 */ 292 #define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \ 293 ((type) == HBN_XCLK_CLK_XTAL)) 294 295 /** @defgroup HBN_ROOT_CLK_TYPE 296 * @{ 297 */ 298 #define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \ 299 ((type) == HBN_ROOT_CLK_XTAL) || \ 300 ((type) == HBN_ROOT_CLK_PLL)) 301 302 /** @defgroup HBN_UART_CLK_TYPE 303 * @{ 304 */ 305 #define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \ 306 ((type) == HBN_UART_CLK_160M)) 307 308 /** @defgroup HBN_RTC_INT_DELAY_TYPE 309 * @{ 310 */ 311 #define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \ 312 ((type) == HBN_RTC_INT_DELAY_0T)) 313 314 /** @defgroup HBN_INT_TYPE 315 * @{ 316 */ 317 #define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO7) || \ 318 ((type) == HBN_INT_GPIO8) || \ 319 ((type) == HBN_INT_RTC) || \ 320 ((type) == HBN_INT_PIR) || \ 321 ((type) == HBN_INT_BOR) || \ 322 ((type) == HBN_INT_ACOMP0) || \ 323 ((type) == HBN_INT_ACOMP1)) 324 325 /** @defgroup HBN_ACOMP_INT_EDGE_TYPE 326 * @{ 327 */ 328 #define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \ 329 ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE)) 330 331 /** @defgroup HBN_GPIO_INT_TRIGGER_TYPE 332 * @{ 333 */ 334 #define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ 335 ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ 336 ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ 337 ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ 338 ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ 339 ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ 340 ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ 341 ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) 342 343 /** @defgroup HBN_OUT0_INT_TYPE 344 * @{ 345 */ 346 #define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO7) || \ 347 ((type) == HBN_OUT0_INT_GPIO8) || \ 348 ((type) == HBN_OUT0_INT_RTC)) 349 350 /** @defgroup HBN_OUT1_INT_TYPE 351 * @{ 352 */ 353 #define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) || \ 354 ((type) == HBN_OUT1_INT_BOR) || \ 355 ((type) == HBN_OUT1_INT_ACOMP0) || \ 356 ((type) == HBN_OUT1_INT_ACOMP1)) 357 358 /** @defgroup HBN_LDO_LEVEL_TYPE 359 * @{ 360 */ 361 #define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \ 362 ((type) == HBN_LDO_LEVEL_0P65V) || \ 363 ((type) == HBN_LDO_LEVEL_0P70V) || \ 364 ((type) == HBN_LDO_LEVEL_0P75V) || \ 365 ((type) == HBN_LDO_LEVEL_0P80V) || \ 366 ((type) == HBN_LDO_LEVEL_0P85V) || \ 367 ((type) == HBN_LDO_LEVEL_0P90V) || \ 368 ((type) == HBN_LDO_LEVEL_0P95V) || \ 369 ((type) == HBN_LDO_LEVEL_1P00V) || \ 370 ((type) == HBN_LDO_LEVEL_1P05V) || \ 371 ((type) == HBN_LDO_LEVEL_1P10V) || \ 372 ((type) == HBN_LDO_LEVEL_1P15V) || \ 373 ((type) == HBN_LDO_LEVEL_1P20V) || \ 374 ((type) == HBN_LDO_LEVEL_1P25V) || \ 375 ((type) == HBN_LDO_LEVEL_1P30V) || \ 376 ((type) == HBN_LDO_LEVEL_1P35V)) 377 378 /** @defgroup HBN_LEVEL_TYPE 379 * @{ 380 */ 381 #define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \ 382 ((type) == HBN_LEVEL_1) || \ 383 ((type) == HBN_LEVEL_2) || \ 384 ((type) == HBN_LEVEL_3)) 385 386 /*@} end of group HBN_Public_Constants */ 387 388 /** @defgroup HBN_Public_Macros 389 * @{ 390 */ 391 #define HBN_RAM_SIZE (4 * 1024) 392 #define HBN_RTC_COMP_BIT0_39 0x01 393 #define HBN_RTC_COMP_BIT0_23 0x02 394 #define HBN_RTC_COMP_BIT13_39 0x04 395 #define HBN_STATUS_ENTER_FLAG 0x4e424845 396 #define HBN_STATUS_WAKEUP_FLAG 0x4e424857 397 #define HBN_WAKEUP_GPIO_NONE 0x00 398 #define HBN_WAKEUP_GPIO_7 0x01 399 #define HBN_WAKEUP_GPIO_8 0x02 400 #define HBN_WAKEUP_GPIO_ALL 0x03 401 402 /*@} end of group HBN_Public_Macros */ 403 404 /** @defgroup HBN_Public_Functions 405 * @{ 406 */ 407 /*----------*/ 408 #ifndef BFLB_USE_HAL_DRIVER 409 void HBN_OUT0_IRQHandler(void); 410 void HBN_OUT1_IRQHandler(void); 411 #endif 412 /*----------*/ 413 void HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg); 414 void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg); 415 void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); 416 BL_Err_Type HBN_Reset(void); 417 BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv); 418 BL_Err_Type HBN_Disable(void); 419 /*----------*/ 420 BL_Err_Type HBN_PIR_Enable(void); 421 BL_Err_Type HBN_PIR_Disable(void); 422 BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg); 423 BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf); 424 BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf); 425 BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold); 426 uint16_t HBN_Get_PIR_Threshold(void); 427 BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval); 428 uint16_t HBN_Get_PIR_Interval(void); 429 /*----------*/ 430 BL_Sts_Type HBN_Get_BOR_OUT_State(void); 431 BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode); 432 /*----------*/ 433 BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel); 434 BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel); 435 BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel); 436 BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel); 437 /*----------*/ 438 BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType); 439 BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel); 440 BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk); 441 HBN_ROOT_CLK_Type HBN_Get_Root_CLK_Sel(void); 442 BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk); 443 /*----------*/ 444 BL_Err_Type HBN_Set_HRAM_slp(void); 445 BL_Err_Type HBN_Set_HRAM_Ret(void); 446 /*----------*/ 447 uint32_t HBN_Get_Status_Flag(void); 448 BL_Err_Type HBN_Set_Status_Flag(uint32_t flag); 449 uint32_t HBN_Get_Wakeup_Addr(void); 450 BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr); 451 /*----------*/ 452 BL_Err_Type HBN_Clear_RTC_Counter(void); 453 BL_Err_Type HBN_Enable_RTC_Counter(void); 454 BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode); 455 BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh); 456 BL_Err_Type HBN_Clear_RTC_INT(void); 457 /*----------*/ 458 BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType); 459 BL_Err_Type HBN_GPIO_INT_Disable(void); 460 BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType); 461 uint8_t HBN_Get_Pin_Wakeup_Mode(void); 462 BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType); 463 BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable); 464 BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg); 465 BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal); 466 /*----------*/ 467 BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); 468 BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); 469 BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); 470 BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); 471 /*----------*/ 472 BL_Err_Type HBN_Enable_BOR_IRQ(void); 473 BL_Err_Type HBN_Disable_BOR_IRQ(void); 474 /*----------*/ 475 BL_Err_Type HBN_Out0_IRQHandler_Install(void); 476 BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun); 477 BL_Err_Type HBN_Out1_IRQHandler_Install(void); 478 BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun); 479 /*----------*/ 480 BL_Err_Type HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, 481 BL_Fun_Type dlyEn, uint8_t dlySec); 482 /*----------*/ 483 BL_Err_Type HBN_Power_On_Xtal_32K(void); 484 BL_Err_Type HBN_Power_Off_Xtal_32K(void); 485 BL_Err_Type HBN_Power_On_RC32K(void); 486 BL_Err_Type HBN_Power_Off_RC32K(void); 487 BL_Err_Type HBN_Trim_RC32K(void); 488 BL_Err_Type HBN_Set_Embedded_Flash_Pullup(uint8_t enable); 489 BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg); 490 491 /*@} end of group HBN_Public_Functions */ 492 493 /*@} end of group HBN */ 494 495 /*@} end of group BL602_Peripheral_Driver */ 496 497 #endif /* __BL602_HBN_H__ */ 498