1 #ifndef __BL702_MEMORYMAP_H
2 #define __BL702_MEMORYMAP_H
3 
4 /****************************************************************************
5  * Included Files
6  ****************************************************************************/
7 
8 /****************************************************************************
9  * Pre-processor Definitions
10  ****************************************************************************/
11 #define BL602_FLASH_XIP_BASE        0x23000000
12 #define BL602_FLASH_XIP_END         (0x23000000 + 16 * 1024 * 1024)
13 #define BL602_FLASH_XIP_REMAP0_BASE 0x33000000
14 #define BL602_FLASH_XIP_REMAP0_END  (0x33000000 + 16 * 1024 * 1024)
15 #define BL602_FLASH_XIP_REMAP1_BASE 0x43000000
16 #define BL602_FLASH_XIP_REMAP1_END  (0x43000000 + 16 * 1024 * 1024)
17 #define BL602_FLASH_XIP_REMAP2_BASE 0x53000000
18 #define BL602_FLASH_XIP_REMAP2_END  (0x53000000 + 16 * 1024 * 1024)
19 
20 #define BL602_WRAM_BASE        0x42020000
21 #define BL602_WRAM_END         (0x42020000 + 176 * 1024)
22 #define BL602_WRAM_REMAP0_BASE 0x22020000
23 #define BL602_WRAM_REMAP0_END  (0x22020000 + 176 * 1024)
24 #define BL602_WRAM_REMAP1_BASE 0x32020000
25 #define BL602_WRAM_REMAP1_END  (0x32020000 + 176 * 1024)
26 #define BL602_WRAM_REMAP2_BASE 0x52020000
27 #define BL602_WRAM_REMAP2_END  (0x52020000 + 176 * 1024)
28 
29 #define BL602_TCM_BASE        0x22008000
30 #define BL602_TCM_END         (0x22008000 + (96 + 176) * 1024)
31 #define BL602_TCM_REMAP0_BASE 0x32008000
32 #define BL602_TCM_REMAP0_END  (0x32008000 + (96 + 176) * 1024)
33 #define BL602_TCM_REMAP1_BASE 0x42008000
34 #define BL602_TCM_REMAP1_END  (0x42008000 + (96 + 176) * 1024)
35 #define BL602_TCM_REMAP2_BASE 0x52008000
36 #define BL602_TCM_REMAP2_END  (0x52008000 + (96 + 176) * 1024)
37 /*@} end of group Memory_Map_Section */
38 
39 /* BL602 peripherals base address */
40 #define GLB_BASE         ((uint32_t)0x40000000)
41 #define RF_BASE          ((uint32_t)0x40001000)
42 #define GPIP_BASE        ((uint32_t)0x40002000) /*!< AUX module base address */
43 #define SEC_DBG_BASE     ((uint32_t)0x40003000) /*!< Security Debug module base address */
44 #define SEC_ENG_BASE     ((uint32_t)0x40004000) /*!< Security Engine module base address */
45 #define TZC_SEC_BASE     ((uint32_t)0x40005000) /*!< Trustzone control security base address */
46 #define TZC_NSEC_BASE    ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */
47 #define EF_DATA_BASE     ((uint32_t)0x40007000)
48 #define EF_CTRL_BASE     ((uint32_t)0x40007000)
49 #define CCI_BASE         ((uint32_t)0x40008000)
50 #define L1C_BASE         ((uint32_t)0x40009000) /*!< L1 cache config base address */
51 #define UART0_BASE       ((uint32_t)0x4000A000)
52 #define UART1_BASE       ((uint32_t)0x4000A100)
53 #define SPI_BASE         ((uint32_t)0x4000A200)
54 #define I2C_BASE         ((uint32_t)0x4000A300)
55 #define PWM_BASE         ((uint32_t)0x4000A400)
56 #define TIMER_BASE       ((uint32_t)0x4000A500)
57 #define IR_BASE          ((uint32_t)0x4000A600)
58 #define SF_CTRL_BASE     ((uint32_t)0x4000B000)
59 #define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
60 #define DMA_BASE         ((uint32_t)0x4000C000)
61 #define SDU_BASE         ((uint32_t)0x4000D000)
62 #define PDS_BASE         ((uint32_t)0x4000E000) /*!< Power down sleep module base address */
63 #define HBN_BASE         ((uint32_t)0x4000F000) /*!< Hibernate module base address */
64 #define AON_BASE         ((uint32_t)0x4000F000) /*!< Always on module base address */
65 #define HBN_RAM_BASE     ((uint32_t)0x40010000)
66 
67 #endif