1 #ifndef __BL616_MEMORYMAP_H 2 #define __BL616_MEMORYMAP_H 3 4 /**************************************************************************** 5 * Included Files 6 ****************************************************************************/ 7 8 /**************************************************************************** 9 * Pre-processor Definitions 10 ****************************************************************************/ 11 #define BL616_OCRAM_BASE (0x20FC0000) 12 #define BL616_OCRAM_END (0x20FC0000 + 320 * 1024) 13 #define BL616_OCRAM_CACHEABLE_BASE (0x60FC0000) 14 #define BL616_OCRAM_CACHEABLE_END (0x60FC0000 + 320 * 1024) 15 #define BL616_OCRAM_BUSREMAP_BASE (0x22FC0000) 16 #define BL616_OCRAM_BUSREMAP_END (0x22FC0000 + 320 * 1024) 17 #define BL616_OCRAM_BUSREMAP_CACHEABLE_BASE (0x62FC0000) 18 #define BL616_OCRAM_BUSREMAP_CACHEABLE_END (0x62FC0000 + 320 * 1024) 19 20 #define BL616_WRAM_BASE (0x21010000) 21 #define BL616_WRAM_END (0x21010000 + 160 * 1024) 22 #define BL616_WRAM_CACHEABLE_BASE (0x61010000) 23 #define BL616_WRAM_CACHEABLE_END (0x61010000 + 160 * 1024) 24 #define BL616_WRAM_BUSREMAP_BASE (0x23010000) 25 #define BL616_WRAM_BUSREMAP_END (0x23010000 + 160 * 1024) 26 #define BL616_WRAM_BUSREMAP_CACHEABLE_BASE (0x63010000) 27 #define BL616_WRAM_BUSREMAP_CACHEABLE_END (0x63010000 + 160 * 1024) 28 29 #define BL616_FLASH_XIP_BASE (0xA0000000) 30 #define BL616_FLASH_XIP_END (0xA0000000 + 64 * 1024 * 1024) 31 #define BL616_FLASH_XIP_REMAP0_BASE (0xD0000000) 32 #define BL616_FLASH_XIP_REMAP0_END (0xD0000000 + 64 * 1024 * 1024) 33 #define BL616_FLASH_XIP_BUSREMAP_BASE (0xA0000000) 34 #define BL616_FLASH_XIP_BUSREMAP_END (0xA0000000 + 64 * 1024 * 1024) 35 36 #define BL616_FLASH2_XIP_BASE (0x84000000) 37 #define BL616_FLASH2_XIP_END (0x84000000 + 64 * 1024 * 1024) 38 #define BL616_FLASH2_XIP_REMAP0_BASE (0xD4000000) 39 #define BL616_FLASH2_XIP_REMAP0_END (0xD4000000 + 64 * 1024 * 1024) 40 #define BL616_FLASH2_XIP_BUSREMAP_BASE (0xA4000000) 41 #define BL616_FLASH2_XIP_BUSREMAP_END (0xA4000000 + 64 * 1024 * 1024) 42 43 #define BL616_PSRAM_BASE (0x88000000) 44 #define BL616_PSRAM_END (0x88000000 + 128 * 1024 * 1024) 45 #define BL616_PSRAM_REMAP0_BASE (0xD8000000) 46 #define BL616_PSRAM_REMAP0_END (0xD8000000 + 128 * 1024 * 1024) 47 #define BL616_PSRAM_BUSREMAP_BASE (0xA8000000) 48 #define BL616_PSRAM_BUSREMAP_END (0xA8000000 + 128 * 1024 * 1024) 49 50 #define BL616_ALLRAM_BASE (0x20FC0000) 51 #define BL616_ALLRAM_END (0x20FC0000 + 320 * 1024 + 160 * 1024) 52 #define BL616_ALLRAM_CACHEABLE_BASE (0x60FC0000) 53 #define BL616_ALLRAM_CACHEABLE_END (0x60FC0000 + 320 * 1024 + 160 * 1024) 54 #define BL616_ALLRAM_BUSREMAP_BASE (0x22FC0000) 55 #define BL616_ALLRAM_BUSREMAP_END (0x22FC0000 + 320 * 1024 + 160 * 1024) 56 #define BL616_ALLRAM_BUSREMAP_CACHEABLE_BASE (0x62FC0000) 57 #define BL616_ALLRAM_BUSREMAP_CACHEABLE_END (0x62FC0000 + 320 * 1024 + 160 * 1024) 58 59 #define GLB_BASE ((uint32_t)0x20000000) 60 #define MIX_BASE ((uint32_t)0x20001000) 61 #define GPIP_BASE ((uint32_t)0x20002000) 62 #define PHY_BASE ((uint32_t)0x20002800) 63 #define AGC_BASE ((uint32_t)0x20002c00) 64 #define SEC_DBG_BASE ((uint32_t)0x20003000) 65 #define SEC_ENG_BASE ((uint32_t)0x20004000) 66 #define TZ1_BASE ((uint32_t)0x20005000) 67 #define TZC_SEC_BASE ((uint32_t)0x20005000) 68 #define TZ2_BASE ((uint32_t)0x20006000) 69 #define TZC_NSEC_BASE ((uint32_t)0x20006000) 70 #define CCI_BASE ((uint32_t)0x20008000) 71 #define MCU_MISC_BASE ((uint32_t)0x20009000) 72 #define L1C_BASE ((uint32_t)0x20009000) 73 #define UART0_BASE ((uint32_t)0x2000a000) 74 #define UART1_BASE ((uint32_t)0x2000a100) 75 #define SPI_BASE ((uint32_t)0x2000a200) 76 #define I2C0_BASE ((uint32_t)0x2000a300) 77 #define PWM_BASE ((uint32_t)0x2000a400) 78 #define TIMER_BASE ((uint32_t)0x2000a500) 79 #define IR_BASE ((uint32_t)0x2000a600) 80 #define CKS_BASE ((uint32_t)0x2000a700) 81 #define DBI_BASE ((uint32_t)0x2000a800) 82 #define I2C1_BASE ((uint32_t)0x2000a900) 83 #define I2S_BASE ((uint32_t)0x2000ab00) 84 #define AUADC_BASE ((uint32_t)0x2000ac00) 85 #define QSPI_BASE ((uint32_t)0x2000b000) 86 #define SF_CTRL_BASE ((uint32_t)0x2000b000) 87 #define SF_CTRL_BUF_BASE ((uint32_t)0x2000b600) 88 #define DMA_BASE ((uint32_t)0x2000c000) 89 #define SDU_BASE ((uint32_t)0x2000d000) 90 #define PDS_BASE ((uint32_t)0x2000e000) 91 #define HBN_BASE ((uint32_t)0x2000f000) 92 #define AON_BASE ((uint32_t)0x2000f000) 93 #define MM_MISC_BASE ((uint32_t)0x20050000) 94 #define PSRAM_CTRL_BASE ((uint32_t)0x20052000) 95 #define AUDAC_BASE ((uint32_t)0x20055000) 96 #define EFUSE_BASE ((uint32_t)0x20056000) 97 #define EF_DATA_BASE ((uint32_t)0x20056000) 98 #define EF_CTRL_BASE ((uint32_t)0x20056000) 99 #define DVP2AXI0_BASE ((uint32_t)0x20057000) 100 #define DVP2AXI1_BASE ((uint32_t)0x20058000) 101 #define MJPEG_BASE ((uint32_t)0x20059000) 102 #define SDH_BASE ((uint32_t)0x20060000) 103 #define EMAC_BASE ((uint32_t)0x20070000) 104 #define USB_BASE ((uint32_t)0x20072000) 105 #define HBN_RAM_BASE ((uint32_t)0x20010000) 106 #define PLFM_DMA_BASE ((uint32_t)0x24A00000) 107 108 #endif