1 /** 2 ****************************************************************************** 3 * @file bl702_glb.h 4 * @version V1.0 5 * @date 6 * @brief This file is the standard driver header file 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __BL702_GLB_H__ 37 #define __BL702_GLB_H__ 38 39 #include "glb_reg.h" 40 #include "pds_reg.h" 41 #include "bl702_gpio.h" 42 #include "bl702_l1c.h" 43 #include "bl702_hbn.h" 44 #include "bl702_aon.h" 45 #include "bl702_ef_ctrl.h" 46 #include "bl702_pds.h" 47 #include "bl702_common.h" 48 #include "bflb_sf_ctrl.h" 49 #include "bflb_sf_cfg.h" 50 51 /** @addtogroup BL702_Peripheral_Driver 52 * @{ 53 */ 54 55 /** @addtogroup GLB 56 * @{ 57 */ 58 59 /** @defgroup GLB_Public_Types 60 * @{ 61 */ 62 63 /** 64 * @brief GLB root clock type definition 65 */ 66 typedef enum { 67 GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */ 68 GLB_ROOT_CLK_XTAL, /*!< root clock select XTAL */ 69 GLB_ROOT_CLK_DLL, /*!< root clock select DLL others, PLL120M not recommend */ 70 } GLB_ROOT_CLK_Type; 71 72 /** 73 * @brief GLB system clock type definition 74 */ 75 typedef enum { 76 GLB_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */ 77 GLB_SYS_CLK_XTAL, /*!< use XTAL as system clock */ 78 GLB_SYS_CLK_DLL57P6M, /*!< use DLL output 57.6M as system clock */ 79 GLB_SYS_CLK_DLL96M, /*!< use DLL output 96M as system clock */ 80 GLB_SYS_CLK_DLL144M, /*!< use DLL output 144M as system clock, PLL120M not recommend */ 81 } GLB_SYS_CLK_Type; 82 83 /** 84 * @brief GLB CAM clock type definition 85 */ 86 typedef enum { 87 GLB_CAM_CLK_XCLK, /*!< Select XCLK as CAM clock */ 88 GLB_CAM_CLK_DLL96M, /*!< Select DLL96M as CAM clock */ 89 } GLB_CAM_CLK_Type; 90 91 /** 92 * @brief GLB I2S output ref clock type definition 93 */ 94 typedef enum { 95 GLB_I2S_OUT_REF_CLK_NONE, /*!< no output reference clock on I2S_0 ref_clock port */ 96 GLB_I2S_OUT_REF_CLK_SRC, /*!< output reference clock on I2S_0 ref_clock port */ 97 } GLB_I2S_OUT_REF_CLK_Type; 98 99 /** 100 * @brief GLB qdec clock type definition 101 */ 102 typedef enum { 103 GLB_QDEC_CLK_XCLK, /*!< Select XCLK as QDEC clock */ 104 GLB_QDEC_CLK_F32K, /*!< Select f32k as QDEC clock (PDS mode) */ 105 } GLB_QDEC_CLK_Type; 106 107 /** 108 * @brief GLB DMA clock ID type definition 109 */ 110 typedef enum { 111 GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */ 112 GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */ 113 GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */ 114 GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */ 115 GLB_DMA_CLK_DMA0_CH4, /*!< DMA clock ID:channel 4 */ 116 GLB_DMA_CLK_DMA0_CH5, /*!< DMA clock ID:channel 5 */ 117 GLB_DMA_CLK_DMA0_CH6, /*!< DMA clock ID:channel 6 */ 118 GLB_DMA_CLK_DMA0_CH7, /*!< DMA clock ID:channel 7 */ 119 } GLB_DMA_CLK_ID_Type; 120 121 /** 122 * @brief GLB clock source type definition 123 */ 124 typedef enum { 125 GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */ 126 } GLB_IR_CLK_SRC_Type; 127 128 /** 129 * @brief GLB flash clock type definition 130 */ 131 typedef enum { 132 GLB_SFLASH_CLK_144M, /*!< Select 144M as flash clock */ 133 GLB_SFLASH_CLK_XCLK, /*!< Select XCLK as flash clock */ 134 GLB_SFLASH_CLK_57P6M, /*!< Select 57.6M as flash clock */ 135 GLB_SFLASH_CLK_72M, /*!< Select 72M as flash clock */ 136 GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */ 137 GLB_SFLASH_CLK_96M, /*!< Select 96M as flash clock */ 138 } GLB_SFLASH_CLK_Type; 139 140 /** 141 * @brief GLB chip clock out type definition 142 */ 143 typedef enum { 144 GLB_CHIP_CLK_OUT_NONE, /*!< no chip clock out */ 145 GLB_CHIP_CLK_OUT_I2S_REF_CLK, /*!< i2s_ref_clk out */ 146 GLB_CHIP_CLK_OUT_AUDIO_PLL_CLK, /*!< audio_pll_clk out */ 147 GLB_CHIP_CLK_OUT_XTAL_SOC_32M, /*!< clk_xtal_soc_32M */ 148 } GLB_CHIP_CLK_OUT_Type; 149 150 /** 151 * @brief GLB eth ref clock out type definition 152 */ 153 typedef enum { 154 GLB_ETH_REF_CLK_OUT_OUTSIDE_50M, /*!< select outside 50MHz RMII ref clock */ 155 GLB_ETH_REF_CLK_OUT_INSIDE_50M, /*!< select inside 50MHz RMII ref clock */ 156 } GLB_ETH_REF_CLK_OUT_Type; 157 158 /** 159 * @brief GLB SPI pad action type definition 160 */ 161 typedef enum { 162 GLB_SPI_PAD_ACT_AS_SLAVE, /*!< SPI pad act as slave */ 163 GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */ 164 } GLB_SPI_PAD_ACT_AS_Type; 165 166 /** 167 * @brief GLB PKA clock type definition 168 */ 169 typedef enum { 170 GLB_PKA_CLK_HCLK, /*!< Select HCLK as PKA clock */ 171 GLB_PKA_CLK_DLL96M, /*!< Select DLL 96M as PKA clock */ 172 } GLB_PKA_CLK_Type; 173 174 /** 175 * @brief BMX arb mode type definition 176 */ 177 typedef enum { 178 BMX_ARB_FIX, /*!< 0->fix */ 179 BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ 180 BMX_ARB_RANDOM, /*!< 3->random */ 181 } BMX_ARB_Type; 182 183 /** 184 * @brief BMX configuration structure type definition 185 */ 186 typedef struct { 187 uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ 188 BL_Fun_Type errEn; /*!< Bus error response enable */ 189 BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ 190 } BMX_Cfg_Type; 191 192 /** 193 * @brief BMX bus err type definition 194 */ 195 typedef enum { 196 BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ 197 BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ 198 } BMX_BUS_ERR_Type; 199 200 /** 201 * @brief BMX bus err interrupt type definition 202 */ 203 typedef enum { 204 BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */ 205 BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */ 206 } BMX_ERR_INT_Type; 207 208 /** 209 * @brief BMX time out interrupt type definition 210 */ 211 typedef enum { 212 BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */ 213 BMX_TO_INT_ALL, /*!< BMX timeout interrupt max num */ 214 } BMX_TO_INT_Type; 215 216 /** 217 * @brief GLB EM type definition 218 */ 219 typedef enum { 220 GLB_EM_0KB = 0x0, /*!< 0x0 --> 0KB */ 221 GLB_EM_8KB = 0x3, /*!< 0x3 --> 8KB */ 222 GLB_EM_16KB = 0xF, /*!< 0xF --> 16KB */ 223 } GLB_EM_Type; 224 225 /** 226 * @brief GLB EMAC and CAM pin type definition 227 */ 228 typedef enum { 229 GLB_EMAC_CAM_PIN_EMAC, /*!< select pin as emac */ 230 GLB_EMAC_CAM_PIN_CAM, /*!< select pin as cam */ 231 } GLB_EMAC_CAM_PIN_Type; 232 233 /** 234 * @brief GLB RTC clock type definition 235 */ 236 typedef enum { 237 GLB_MTIMER_CLK_BCLK, /*!< BUS clock */ 238 GLB_MTIMER_CLK_32K, /*!< 32KHz */ 239 } GLB_MTIMER_CLK_Type; 240 241 /** 242 * @brief GLB ADC clock type definition 243 */ 244 typedef enum { 245 GLB_ADC_CLK_AUDIO_PLL, /*!< use Audio PLL as ADC clock */ 246 GLB_ADC_CLK_XCLK, /*!< use XCLK as ADC clock */ 247 } GLB_ADC_CLK_Type; 248 249 /** 250 * @brief GLB DAC clock type definition 251 */ 252 typedef enum { 253 GLB_DAC_CLK_PLL_32M, /*!< select PLL 32M as DAC clock source */ 254 GLB_DAC_CLK_XCLK, /*!< select XCLK as DAC clock source */ 255 GLB_DAC_CLK_AUDIO_PLL, /*!< select Audio PLL as DAC clock source */ 256 } GLB_DAC_CLK_Type; 257 258 /** 259 * @brief GLB DIG clock source select type definition 260 */ 261 typedef enum { 262 GLB_DIG_CLK_PLL_32M, /*!< select PLL 32M as DIG clock source */ 263 GLB_DIG_CLK_XCLK, /*!< select XCLK as DIG clock source */ 264 GLB_DIG_CLK_AUDIO_PLL, /*!< select Audio PLL as DIG clock source */ 265 } GLB_DIG_CLK_Type; 266 267 /** 268 * @brief GLB BT bandwidth type definition 269 */ 270 typedef enum { 271 GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */ 272 GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */ 273 } GLB_BT_BANDWIDTH_Type; 274 275 /** 276 * @brief GLB UART signal type definition 277 */ 278 typedef enum { 279 GLB_UART_SIG_0, /*!< UART signal 0 */ 280 GLB_UART_SIG_1, /*!< UART signal 1 */ 281 GLB_UART_SIG_2, /*!< UART signal 2 */ 282 GLB_UART_SIG_3, /*!< UART signal 3 */ 283 GLB_UART_SIG_4, /*!< UART signal 4 */ 284 GLB_UART_SIG_5, /*!< UART signal 5 */ 285 GLB_UART_SIG_6, /*!< UART signal 6 */ 286 GLB_UART_SIG_7, /*!< UART signal 7 */ 287 } GLB_UART_SIG_Type; 288 289 /** 290 * @brief GLB UART signal function type definition 291 */ 292 typedef enum { 293 GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */ 294 GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */ 295 GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */ 296 GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */ 297 GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */ 298 GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */ 299 GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */ 300 GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */ 301 } GLB_UART_SIG_FUN_Type; 302 303 /** 304 * @brief GLB DLL output clock type definition 305 */ 306 typedef enum { 307 GLB_DLL_CLK_57P6M, /*!< DLL output 57P6M clock */ 308 GLB_DLL_CLK_96M, /*!< DLL output 96M clock */ 309 GLB_DLL_CLK_144M, /*!< DLL output 144M clock */ 310 GLB_DLL_CLK_288M, /*!< DLL output 288M clock */ 311 GLB_DLL_CLK_MMDIV, /*!< DLL output mmdiv clock */ 312 } GLB_DLL_CLK_Type; 313 314 /** 315 * @brief GLB GPIO interrupt trigger mode type definition 316 */ 317 typedef enum { 318 GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */ 319 GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */ 320 GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */ 321 GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */ 322 } GLB_GPIO_INT_TRIG_Type; 323 324 /** 325 * @brief GLB GPIO interrupt control mode type definition 326 */ 327 typedef enum { 328 GLB_GPIO_INT_CONTROL_SYNC, /*!< GPIO interrupt sync mode */ 329 GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */ 330 } GLB_GPIO_INT_CONTROL_Type; 331 332 /** 333 * @brief PLL XTAL type definition 334 */ 335 typedef enum { 336 GLB_DLL_XTAL_NONE, /*!< XTAL is none */ 337 GLB_DLL_XTAL_32M, /*!< XTAL is 32M */ 338 GLB_DLL_XTAL_RC32M, /*!< XTAL is RC32M */ 339 } GLB_DLL_XTAL_Type; 340 341 typedef enum { 342 GLB_AHB_CLOCK_IP_CPU, 343 GLB_AHB_CLOCK_IP_SDU, 344 GLB_AHB_CLOCK_IP_SEC, 345 GLB_AHB_CLOCK_IP_DMA_0, 346 GLB_AHB_CLOCK_IP_DMA_1, 347 GLB_AHB_CLOCK_IP_DMA_2, 348 GLB_AHB_CLOCK_IP_CCI, 349 GLB_AHB_CLOCK_IP_RF_TOP, 350 GLB_AHB_CLOCK_IP_GPIP, 351 GLB_AHB_CLOCK_IP_TZC, 352 GLB_AHB_CLOCK_IP_EF_CTRL, 353 GLB_AHB_CLOCK_IP_SF_CTRL, 354 GLB_AHB_CLOCK_IP_EMAC, 355 GLB_AHB_CLOCK_IP_UART0, 356 GLB_AHB_CLOCK_IP_UART1, 357 GLB_AHB_CLOCK_IP_UART2, 358 GLB_AHB_CLOCK_IP_UART3, 359 GLB_AHB_CLOCK_IP_UART4, 360 GLB_AHB_CLOCK_IP_SPI, 361 GLB_AHB_CLOCK_IP_I2C, 362 GLB_AHB_CLOCK_IP_PWM, 363 GLB_AHB_CLOCK_IP_TIMER, 364 GLB_AHB_CLOCK_IP_IR, 365 GLB_AHB_CLOCK_IP_CHECKSUM, 366 GLB_AHB_CLOCK_IP_QDEC, 367 GLB_AHB_CLOCK_IP_KYS, 368 GLB_AHB_CLOCK_IP_I2S, 369 GLB_AHB_CLOCK_IP_USB11, 370 GLB_AHB_CLOCK_IP_CAM, 371 GLB_AHB_CLOCK_IP_MJPEG, 372 GLB_AHB_CLOCK_IP_BT_BLE_NORMAL, 373 GLB_AHB_CLOCK_IP_BT_BLE_LP, 374 GLB_AHB_CLOCK_IP_ZB_NORMAL, 375 GLB_AHB_CLOCK_IP_ZB_LP, 376 GLB_AHB_CLOCK_IP_WIFI_NORMAL, 377 GLB_AHB_CLOCK_IP_WIFI_LP, 378 GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL, 379 GLB_AHB_CLOCK_IP_BT_BLE_2_LP, 380 GLB_AHB_CLOCK_IP_EMI_MISC, 381 GLB_AHB_CLOCK_IP_PSRAM0_CTRL, 382 GLB_AHB_CLOCK_IP_PSRAM1_CTRL, 383 GLB_AHB_CLOCK_IP_USB20, 384 GLB_AHB_CLOCK_IP_MIX2, 385 GLB_AHB_CLOCK_IP_AUDIO, 386 GLB_AHB_CLOCK_IP_SDH, 387 } GLB_AHB_CLOCK_IP_Type; 388 389 /*@} end of group GLB_Public_Types */ 390 391 /** @defgroup GLB_Public_Constants 392 * @{ 393 */ 394 395 /** @defgroup GLB_ROOT_CLK_TYPE 396 * @{ 397 */ 398 #define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \ 399 ((type) == GLB_ROOT_CLK_XTAL) || \ 400 ((type) == GLB_ROOT_CLK_DLL)) 401 402 /** @defgroup GLB_SYS_CLK_TYPE 403 * @{ 404 */ 405 #define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) || \ 406 ((type) == GLB_SYS_CLK_XTAL) || \ 407 ((type) == GLB_SYS_CLK_DLL57P6M) || \ 408 ((type) == GLB_SYS_CLK_DLL96M) || \ 409 ((type) == GLB_SYS_CLK_DLL144M)) 410 411 /** @defgroup GLB_CAM_CLK_TYPE 412 * @{ 413 */ 414 #define IS_GLB_CAM_CLK_TYPE(type) (((type) == GLB_CAM_CLK_XCLK) || \ 415 ((type) == GLB_CAM_CLK_DLL96M)) 416 417 /** @defgroup GLB_I2S_OUT_REF_CLK_TYPE 418 * @{ 419 */ 420 #define IS_GLB_I2S_OUT_REF_CLK_TYPE(type) (((type) == GLB_I2S_OUT_REF_CLK_NONE) || \ 421 ((type) == GLB_I2S_OUT_REF_CLK_SRC)) 422 423 /** @defgroup GLB_QDEC_CLK_TYPE 424 * @{ 425 */ 426 #define IS_GLB_QDEC_CLK_TYPE(type) (((type) == GLB_QDEC_CLK_XCLK) || \ 427 ((type) == GLB_QDEC_CLK_F32K)) 428 429 /** @defgroup GLB_DMA_CLK_ID_TYPE 430 * @{ 431 */ 432 #define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \ 433 ((type) == GLB_DMA_CLK_DMA0_CH1) || \ 434 ((type) == GLB_DMA_CLK_DMA0_CH2) || \ 435 ((type) == GLB_DMA_CLK_DMA0_CH3) || \ 436 ((type) == GLB_DMA_CLK_DMA0_CH4) || \ 437 ((type) == GLB_DMA_CLK_DMA0_CH5) || \ 438 ((type) == GLB_DMA_CLK_DMA0_CH6) || \ 439 ((type) == GLB_DMA_CLK_DMA0_CH7)) 440 441 /** @defgroup GLB_IR_CLK_SRC_TYPE 442 * @{ 443 */ 444 #define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK)) 445 446 /** @defgroup GLB_SFLASH_CLK_TYPE 447 * @{ 448 */ 449 #define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_144M) || \ 450 ((type) == GLB_SFLASH_CLK_XCLK) || \ 451 ((type) == GLB_SFLASH_CLK_57P6M) || \ 452 ((type) == GLB_SFLASH_CLK_72M) || \ 453 ((type) == GLB_SFLASH_CLK_BCLK) || \ 454 ((type) == GLB_SFLASH_CLK_96M)) 455 456 /** @defgroup GLB_CHIP_CLK_OUT_TYPE 457 * @{ 458 */ 459 #define IS_GLB_CHIP_CLK_OUT_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_NONE) || \ 460 ((type) == GLB_CHIP_CLK_OUT_I2S_REF_CLK) || \ 461 ((type) == GLB_CHIP_CLK_OUT_AUDIO_PLL_CLK) || \ 462 ((type) == GLB_CHIP_CLK_OUT_XTAL_SOC_32M)) 463 464 /** @defgroup GLB_ETH_REF_CLK_OUT_TYPE 465 * @{ 466 */ 467 #define IS_GLB_ETH_REF_CLK_OUT_TYPE(type) (((type) == GLB_ETH_REF_CLK_OUT_OUTSIDE_50M) || \ 468 ((type) == GLB_ETH_REF_CLK_OUT_INSIDE_50M)) 469 470 /** @defgroup GLB_SPI_PAD_ACT_AS_TYPE 471 * @{ 472 */ 473 #define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \ 474 ((type) == GLB_SPI_PAD_ACT_AS_MASTER)) 475 476 /** @defgroup GLB_PKA_CLK_TYPE 477 * @{ 478 */ 479 #define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \ 480 ((type) == GLB_PKA_CLK_DLL96M)) 481 482 /** @defgroup BMX_ARB_TYPE 483 * @{ 484 */ 485 #define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) || \ 486 ((type) == BMX_ARB_ROUND_ROBIN) || \ 487 ((type) == BMX_ARB_RANDOM)) 488 489 /** @defgroup BMX_BUS_ERR_TYPE 490 * @{ 491 */ 492 #define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \ 493 ((type) == BMX_BUS_ERR_ADDR_DECODE)) 494 495 /** @defgroup BMX_ERR_INT_TYPE 496 * @{ 497 */ 498 #define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \ 499 ((type) == BMX_ERR_INT_ALL)) 500 501 /** @defgroup BMX_TO_INT_TYPE 502 * @{ 503 */ 504 #define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \ 505 ((type) == BMX_TO_INT_ALL)) 506 507 /** @defgroup GLB_EM_TYPE 508 * @{ 509 */ 510 #define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \ 511 ((type) == GLB_EM_8KB) || \ 512 ((type) == GLB_EM_16KB)) 513 514 /** @defgroup GLB_EMAC_CAM_PIN_TYPE 515 * @{ 516 */ 517 #define IS_GLB_EMAC_CAM_PIN_TYPE(type) (((type) == GLB_EMAC_CAM_PIN_EMAC) || \ 518 ((type) == GLB_EMAC_CAM_PIN_CAM)) 519 520 /** @defgroup GLB_MTIMER_CLK_TYPE 521 * @{ 522 */ 523 #define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \ 524 ((type) == GLB_MTIMER_CLK_32K)) 525 526 /** @defgroup GLB_ADC_CLK_TYPE 527 * @{ 528 */ 529 #define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_AUDIO_PLL) || \ 530 ((type) == GLB_ADC_CLK_XCLK)) 531 532 /** @defgroup GLB_DAC_CLK_TYPE 533 * @{ 534 */ 535 #define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_PLL_32M) || \ 536 ((type) == GLB_DAC_CLK_XCLK) || \ 537 ((type) == GLB_DAC_CLK_AUDIO_PLL)) 538 539 /** @defgroup GLB_DIG_CLK_TYPE 540 * @{ 541 */ 542 #define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \ 543 ((type) == GLB_DIG_CLK_XCLK) || \ 544 ((type) == GLB_DIG_CLK_AUDIO_PLL)) 545 546 /** @defgroup GLB_BT_BANDWIDTH_TYPE 547 * @{ 548 */ 549 #define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \ 550 ((type) == GLB_BT_BANDWIDTH_2M)) 551 552 /** @defgroup GLB_UART_SIG_TYPE 553 * @{ 554 */ 555 #define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \ 556 ((type) == GLB_UART_SIG_1) || \ 557 ((type) == GLB_UART_SIG_2) || \ 558 ((type) == GLB_UART_SIG_3) || \ 559 ((type) == GLB_UART_SIG_4) || \ 560 ((type) == GLB_UART_SIG_5) || \ 561 ((type) == GLB_UART_SIG_6) || \ 562 ((type) == GLB_UART_SIG_7)) 563 564 /** @defgroup GLB_UART_SIG_FUN_TYPE 565 * @{ 566 */ 567 #define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \ 568 ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \ 569 ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \ 570 ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \ 571 ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \ 572 ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \ 573 ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \ 574 ((type) == GLB_UART_SIG_FUN_UART1_RXD)) 575 576 /** @defgroup GLB_DLL_CLK_TYPE 577 * @{ 578 */ 579 #define IS_GLB_DLL_CLK_TYPE(type) (((type) == GLB_DLL_CLK_57P6M) || \ 580 ((type) == GLB_DLL_CLK_96M) || \ 581 ((type) == GLB_DLL_CLK_144M) || \ 582 ((type) == GLB_DLL_CLK_288M) || \ 583 ((type) == GLB_DLL_CLK_MMDIV)) 584 585 /** @defgroup GLB_GPIO_INT_TRIG_TYPE 586 * @{ 587 */ 588 #define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \ 589 ((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \ 590 ((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \ 591 ((type) == GLB_GPIO_INT_TRIG_POS_LEVEL)) 592 593 /** @defgroup GLB_GPIO_INT_CONTROL_TYPE 594 * @{ 595 */ 596 #define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \ 597 ((type) == GLB_GPIO_INT_CONTROL_ASYNC)) 598 599 /** @defgroup GLB_DLL_XTAL_TYPE 600 * @{ 601 */ 602 #define IS_GLB_DLL_XTAL_TYPE(type) (((type) == GLB_DLL_XTAL_NONE) || \ 603 ((type) == GLB_DLL_XTAL_32M) || \ 604 ((type) == GLB_DLL_XTAL_RC32M)) 605 606 /*@} end of group GLB_Public_Constants */ 607 608 /** @defgroup GLB_Public_Macros 609 * @{ 610 */ 611 #define UART_SIG_SWAP_GPIO0_GPIO7 0x01 /* GPIO0-7 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ 612 #define UART_SIG_SWAP_GPIO8_GPIO15 0x02 /* GPIO8-15 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ 613 #define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */ 614 #define UART_SIG_SWAP_NONE 0x00 /* GPIO0-22 uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */ 615 #define JTAG_SIG_SWAP_GPIO0_GPIO3 0x01 /* GPIO0-3 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 616 #define JTAG_SIG_SWAP_GPIO4_GPIO7 0x02 /* GPIO4-7 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 617 #define JTAG_SIG_SWAP_GPIO8_GPIO11 0x04 /* GPIO8-11 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 618 #define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 619 #define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 620 #define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 621 #define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */ 622 623 #define GLB_AHB_CLOCK_CPU (0x0000000000000001UL) 624 #define GLB_AHB_CLOCK_SDU (0x0000000000000002UL) 625 #define GLB_AHB_CLOCK_SEC (0x0000000000000004UL) 626 #define GLB_AHB_CLOCK_DMA_0 (0x0000000000000008UL) 627 #define GLB_AHB_CLOCK_DMA_1 (0x0000000000000010UL) 628 #define GLB_AHB_CLOCK_DMA_2 (0x0000000000000020UL) 629 #define GLB_AHB_CLOCK_CCI (0x0000000000000040UL) 630 #define GLB_AHB_CLOCK_RF_TOP (0x0000000000000080UL) 631 #define GLB_AHB_CLOCK_GPIP (0x0000000000000100UL) 632 #define GLB_AHB_CLOCK_TZC (0x0000000000000200UL) 633 #define GLB_AHB_CLOCK_EF_CTRL (0x0000000000000400UL) 634 #define GLB_AHB_CLOCK_SF_CTRL (0x0000000000000800UL) 635 #define GLB_AHB_CLOCK_EMAC (0x0000000000001000UL) 636 #define GLB_AHB_CLOCK_UART0 (0x0000000000002000UL) 637 #define GLB_AHB_CLOCK_UART1 (0x0000000000004000UL) 638 #define GLB_AHB_CLOCK_UART2 (0x0000000000008000UL) 639 #define GLB_AHB_CLOCK_UART3 (0x0000000000010000UL) 640 #define GLB_AHB_CLOCK_UART4 (0x0000000000020000UL) 641 #define GLB_AHB_CLOCK_SPI (0x0000000000040000UL) 642 #define GLB_AHB_CLOCK_I2C (0x0000000000080000UL) 643 #define GLB_AHB_CLOCK_PWM (0x0000000000100000UL) 644 #define GLB_AHB_CLOCK_TIMER (0x0000000000200000UL) 645 #define GLB_AHB_CLOCK_IR (0x0000000000400000UL) 646 #define GLB_AHB_CLOCK_CHECKSUM (0x0000000000800000UL) 647 #define GLB_AHB_CLOCK_QDEC (0x0000000001000000UL) 648 #define GLB_AHB_CLOCK_KYS (0x0000000002000000UL) 649 #define GLB_AHB_CLOCK_I2S (0x0000000004000000UL) 650 #define GLB_AHB_CLOCK_USB11 (0x0000000008000000UL) 651 #define GLB_AHB_CLOCK_CAM (0x0000000010000000UL) 652 #define GLB_AHB_CLOCK_MJPEG (0x0000000020000000UL) 653 #define GLB_AHB_CLOCK_BT_BLE_NORMAL (0x0000000040000000UL) 654 #define GLB_AHB_CLOCK_BT_BLE_LP (0x0000000080000000UL) 655 #define GLB_AHB_CLOCK_ZB_NORMAL (0x0000000100000000UL) 656 #define GLB_AHB_CLOCK_ZB_LP (0x0000000200000000UL) 657 #define GLB_AHB_CLOCK_WIFI_NORMAL (0x0000000400000000UL) 658 #define GLB_AHB_CLOCK_WIFI_LP (0x0000000800000000UL) 659 #define GLB_AHB_CLOCK_BT_BLE_2_NORMAL (0x0000001000000000UL) 660 #define GLB_AHB_CLOCK_BT_BLE_2_LP (0x0000002000000000UL) 661 #define GLB_AHB_CLOCK_EMI_MISC (0x0000004000000000UL) 662 #define GLB_AHB_CLOCK_PSRAM0_CTRL (0x0000008000000000UL) 663 #define GLB_AHB_CLOCK_PSRAM1_CTRL (0x0000010000000000UL) 664 #define GLB_AHB_CLOCK_USB20 (0x0000020000000000UL) 665 #define GLB_AHB_CLOCK_MIX2 (0x0000040000000000UL) 666 #define GLB_AHB_CLOCK_AUDIO (0x0000080000000000UL) 667 #define GLB_AHB_CLOCK_SDH (0x0000100000000000UL) 668 669 /*@} end of group GLB_Public_Macros */ 670 671 /** @defgroup GLB_Public_Functions 672 * @{ 673 */ 674 /*----------*/ 675 #ifndef BFLB_USE_HAL_DRIVER 676 void BMX_ERR_IRQHandler(void); 677 void BMX_TO_IRQHandler(void); 678 void GPIO_INT0_IRQHandler(void); 679 #endif 680 /*----------*/ 681 GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void); 682 BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv); 683 uint8_t GLB_Get_BCLK_Div(void); 684 uint8_t GLB_Get_HCLK_Div(void); 685 BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType); 686 BL_Err_Type GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq); 687 BL_Err_Type System_Core_Clock_Update_From_RC32M(void); 688 /*----------*/ 689 BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div); 690 BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable); 691 BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable); 692 BL_Err_Type GLB_Set_I2S_CLK(uint8_t enable, GLB_I2S_OUT_REF_CLK_Type outRef); 693 BL_Err_Type GLB_Set_USB_CLK(uint8_t enable); 694 BL_Err_Type GLB_Set_QDEC_CLK(GLB_QDEC_CLK_Type clkSel, uint8_t div); 695 /*----------*/ 696 BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk); 697 BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div); 698 BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div); 699 BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div); 700 /*----------*/ 701 BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel); 702 BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel); 703 BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div); 704 BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable); 705 BL_Err_Type GLB_Invert_RF_TEST_O_CLK(uint8_t enable); 706 BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div); 707 BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable); 708 BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable); 709 BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel); 710 /*----------*/ 711 BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel); 712 BL_Err_Type GLB_SW_System_Reset(void); 713 BL_Err_Type GLB_SW_CPU_Reset(void); 714 BL_Err_Type GLB_SW_POR_Reset(void); 715 BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1); 716 BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1); 717 uint64_t GLB_PER_Clock_Gate_Status_Get(void); 718 BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips); 719 BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips); 720 /*----------*/ 721 BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg); 722 BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void); 723 BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void); 724 BL_Err_Type GLB_BMX_BusErrResponse_Enable(void); 725 BL_Err_Type GLB_BMX_BusErrResponse_Disable(void); 726 BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType); 727 uint32_t GLB_BMX_Get_Err_Addr(void); 728 BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun); 729 BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun); 730 /*----------*/ 731 BL_Err_Type GLB_Set_SRAM_RET(uint32_t value); 732 uint32_t GLB_Get_SRAM_RET(void); 733 BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value); 734 uint32_t GLB_Get_SRAM_SLP(void); 735 BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value); 736 uint32_t GLB_Get_SRAM_PARM(void); 737 /*----------*/ 738 BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType); 739 /*----------*/ 740 BL_Err_Type GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_Type pinType); 741 BL_Err_Type GLB_Set_Ext_Rst_Smt(uint8_t enable); 742 BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable); 743 BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel); 744 BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel); 745 BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable); 746 BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable); 747 BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState); 748 BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod); 749 BL_Err_Type GLB_Select_Internal_Flash(void); 750 BL_Err_Type GLB_Select_External_Flash(void); 751 BL_Err_Type GLB_Deswap_Flash_Pin(void); 752 BL_Err_Type GLB_Swap_Flash_CS_IO2_Pin(); 753 BL_Err_Type GLB_Swap_Flash_IO0_IO3_Pin(); 754 BL_Err_Type GLB_Swap_Flash_Pin(void); 755 BL_Err_Type GLB_Select_Internal_PSram(void); 756 /*----------*/ 757 BL_Err_Type GLB_Set_PDM_CLK(uint8_t enable, uint8_t div); 758 /*----------*/ 759 BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div); 760 /*----------*/ 761 BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div); 762 BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div); 763 /*----------*/ 764 BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel); 765 BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div); 766 BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint16_t div); 767 /*----------*/ 768 BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, 769 uint8_t pti, uint8_t channel); 770 /*----------*/ 771 BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun); 772 /*----------*/ 773 BL_Err_Type GLB_Power_Off_DLL(void); 774 BL_Err_Type GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType); 775 BL_Err_Type GLB_Enable_DLL_All_Clks(void); 776 BL_Err_Type GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk); 777 BL_Err_Type GLB_Disable_DLL_All_Clks(void); 778 BL_Err_Type GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk); 779 /*----------*/ 780 BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio); 781 BL_Err_Type GLB_IR_LED_Driver_Enable(void); 782 BL_Err_Type GLB_IR_LED_Driver_Disable(void); 783 BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_GPIO_Type gpio); 784 BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_GPIO_Type gpio); 785 BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias); 786 /*----------*/ 787 BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg); 788 BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt); 789 BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin); 790 BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin); 791 BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin); 792 BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin); 793 BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin); 794 BL_Err_Type GLB_Set_Flash_Pad_HZ(void); 795 BL_Err_Type GLB_Set_Psram_Pad_HZ(void); 796 uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin); 797 BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val); 798 uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin); 799 BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask); 800 BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear); 801 BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin); 802 BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, 803 GLB_GPIO_INT_TRIG_Type intTrgMod); 804 GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin); 805 BL_Err_Type GLB_GPIO_Int2Mask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask); 806 BL_Err_Type GLB_GPIO_Int2Clear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear); 807 BL_Sts_Type GLB_Get_GPIO_Int2Status(GLB_GPIO_Type gpioPin); 808 BL_Err_Type GLB_Set_GPIO_Int2Mod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, 809 GLB_GPIO_INT_TRIG_Type intTrgMod); 810 GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_Int2CtlMod(GLB_GPIO_Type gpioPin); 811 BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void); 812 BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun); 813 BL_Err_Type GLB_GPIO_INT0_Callback_Install2(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun); 814 /*----------*/; 815 816 /*@} end of group GLB_Public_Functions */ 817 818 /*@} end of group GLB */ 819 820 /*@} end of group BL702_Peripheral_Driver */ 821 822 #endif /* __BL702_GLB_H__ */ 823