1 /** 2 ****************************************************************************** 3 * @file bl702_hbn.h 4 * @version V1.0 5 * @date 6 * @brief This file is the standard driver header file 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __BL702_HBN_H__ 37 #define __BL702_HBN_H__ 38 39 #include "hbn_reg.h" 40 #include "bl702_aon.h" 41 #include "bl702_common.h" 42 #include "bflb_sflash.h" 43 44 /** @addtogroup BL702_Peripheral_Driver 45 * @{ 46 */ 47 48 /** @addtogroup HBN 49 * @{ 50 */ 51 52 /** @defgroup HBN_Public_Types 53 * @{ 54 */ 55 56 /** 57 * @brief HBN PIR interrupt configuration type definition 58 */ 59 typedef struct 60 { 61 BL_Fun_Type lowIntEn; /*!< Low will trigger interrupt */ 62 BL_Fun_Type highIntEn; /*!< High will trigger interrupt */ 63 } HBN_PIR_INT_CFG_Type; 64 65 /** 66 * @brief HBN PIR low pass filter type definition 67 */ 68 typedef enum { 69 HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */ 70 HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */ 71 } HBN_PIR_LPF_Type; 72 73 /** 74 * @brief HBN PIR high pass filter type definition 75 */ 76 typedef enum { 77 HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */ 78 HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */ 79 HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */ 80 } HBN_PIR_HPF_Type; 81 82 /** 83 * @brief HBN BOR threshold type definition 84 */ 85 typedef enum { 86 HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */ 87 HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */ 88 } HBN_BOR_THRES_Type; 89 90 /** 91 * @brief HBN BOR mode type definition 92 */ 93 typedef enum { 94 HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */ 95 HBN_BOR_MODE_POR_RELEVANT, /*!< POR is relevant to BOR */ 96 } HBN_BOR_MODE_Type; 97 98 /** 99 * @brief HBN 32K clock type definition 100 */ 101 typedef enum { 102 HBN_32K_RC = 0, /*!< HBN use rc 32k */ 103 HBN_32K_XTAL, /*!< HBN use xtal 32k */ 104 HBN_32K_DIG = 3, /*!< HBN use dig 32k */ 105 } HBN_32K_CLK_Type; 106 107 /** 108 * @brief HBN xclk clock type definition 109 */ 110 typedef enum { 111 HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */ 112 HBN_XCLK_CLK_XTAL, /*!< use XTAL as xclk clock */ 113 } HBN_XCLK_CLK_Type; 114 115 /** 116 * @brief HBN root clock type definition 117 */ 118 typedef enum { 119 HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */ 120 HBN_ROOT_CLK_XTAL, /*!< use XTAL as root clock */ 121 HBN_ROOT_CLK_DLL, /*!< use DLL as root clock */ 122 } HBN_ROOT_CLK_Type; 123 124 /** 125 * @brief HBN UART clock type definition 126 */ 127 typedef enum { 128 HBN_UART_CLK_FCLK = 0, /*!< Select FCLK as UART clock */ 129 HBN_UART_CLK_96M, /*!< Select 96M as UART clock */ 130 } HBN_UART_CLK_Type; 131 132 /** 133 * @brief HBN RTC interrupt delay type definition 134 */ 135 typedef enum { 136 HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */ 137 HBN_RTC_INT_DELAY_0T = 1, /*!< HBN RTC interrupt delay 0T */ 138 } HBN_RTC_INT_Delay_Type; 139 140 /** 141 * @brief HBN interrupt type definition 142 */ 143 typedef enum { 144 HBN_INT_GPIO9 = 0, /*!< HBN interrupt type: GPIO9 */ 145 HBN_INT_GPIO10 = 1, /*!< HBN interrupt type: GPIO10 */ 146 HBN_INT_GPIO11 = 2, /*!< HBN interrupt type: GPIO11 */ 147 HBN_INT_GPIO12 = 3, /*!< HBN interrupt type: GPIO12 */ 148 HBN_INT_GPIO13 = 4, /*!< HBN interrupt type: GPIO13 */ 149 HBN_INT_RTC = 16, /*!< HBN interrupt type: RTC */ 150 HBN_INT_PIR, /*!< HBN interrupt type: PIR */ 151 HBN_INT_BOR, /*!< HBN interrupt type: BOR */ 152 HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */ 153 HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */ 154 } HBN_INT_Type; 155 156 /** 157 * @brief HBN acomp interrupt type definition 158 */ 159 typedef enum { 160 HBN_ACOMP_INT_EDGE_POSEDGE = 0, /*!< HBN acomp interrupt edge posedge */ 161 HBN_ACOMP_INT_EDGE_NEGEDGE = 1, /*!< HBN acomp interrupt edge negedge */ 162 } HBN_ACOMP_INT_EDGE_Type; 163 164 /** 165 * @brief HBN reset event type definition 166 */ 167 typedef enum { 168 HBN_RST_EVENT_POR_OUT, /*!< por_out event */ 169 HBN_RST_EVENT_EXT_RST_N, /*!< ext_rst_n event */ 170 HBN_RST_EVENT_SW_RST, /*!< sw_rst event */ 171 HBN_RST_EVENT_PWR_RST_N, /*!< pwr_rst_n event */ 172 HBN_RST_EVENT_BOR_OUT, /*!< bor_out_ event */ 173 } HBN_RST_EVENT_Type; 174 175 /** 176 * @brief HBN GPIO interrupt trigger type definition 177 */ 178 typedef enum { 179 HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: sync falling edge trigger */ 180 HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: sync rising edge trigger */ 181 HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: sync low level trigger */ 182 HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: sync high level trigger */ 183 HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */ 184 HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: async rising edge trigger */ 185 HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: async low level trigger */ 186 HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: async high level trigger */ 187 } HBN_GPIO_INT_Trigger_Type; 188 189 /** 190 * @brief HBN OUT0 interrupt type definition 191 */ 192 typedef enum { 193 HBN_OUT0_INT_GPIO9 = 0, /*!< HBN out 0 interrupt type: GPIO9 */ 194 HBN_OUT0_INT_GPIO10 = 1, /*!< HBN out 0 interrupt type: GPIO10 */ 195 HBN_OUT0_INT_GPIO11 = 2, /*!< HBN out 0 interrupt type: GPIO11 */ 196 HBN_OUT0_INT_GPIO12 = 3, /*!< HBN out 0 interrupt type: GPIO12 */ 197 HBN_OUT0_INT_GPIO13 = 4, /*!< HBN out 0 interrupt type: GPIO13 */ 198 HBN_OUT0_INT_RTC, /*!< HBN out 0 interrupt type: RTC */ 199 HBN_OUT0_MAX, /*!< HBN out 0 max num */ 200 } HBN_OUT0_INT_Type; 201 202 /** 203 * @brief HBN OUT0 interrupt type definition 204 */ 205 typedef enum { 206 HBN_OUT1_INT_PIR, /*!< HBN out 1 interrupt type: PIR */ 207 HBN_OUT1_INT_BOR, /*!< HBN out 1 interrupt type: BOR */ 208 HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */ 209 HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */ 210 HBN_OUT1_MAX, /*!< HBN out 1 max num */ 211 } HBN_OUT1_INT_Type; 212 213 /** 214 * @brief HBN LDO level type definition 215 */ 216 typedef enum { 217 HBN_LDO_LEVEL_0P60V = 0, /*!< HBN LDO voltage 0.60V */ 218 HBN_LDO_LEVEL_0P65V = 1, /*!< HBN LDO voltage 0.65V */ 219 HBN_LDO_LEVEL_0P70V = 2, /*!< HBN LDO voltage 0.70V */ 220 HBN_LDO_LEVEL_0P75V = 3, /*!< HBN LDO voltage 0.75V */ 221 HBN_LDO_LEVEL_0P80V = 4, /*!< HBN LDO voltage 0.80V */ 222 HBN_LDO_LEVEL_0P85V = 5, /*!< HBN LDO voltage 0.85V */ 223 HBN_LDO_LEVEL_0P90V = 6, /*!< HBN LDO voltage 0.90V */ 224 HBN_LDO_LEVEL_0P95V = 7, /*!< HBN LDO voltage 0.95V */ 225 HBN_LDO_LEVEL_1P00V = 8, /*!< HBN LDO voltage 1.00V */ 226 HBN_LDO_LEVEL_1P05V = 9, /*!< HBN LDO voltage 1.05V */ 227 HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */ 228 HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */ 229 HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */ 230 HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */ 231 HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */ 232 HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */ 233 } HBN_LDO_LEVEL_Type; 234 235 /** 236 * @brief HBN LDO11RT drive strength type definition 237 */ 238 typedef enum { 239 HBN_LDO11RT_DRIVE_STRENGTH_5_50UA = 0, /*!< HBN LDO11RT drive strength 0: 5uA to 50uA */ 240 HBN_LDO11RT_DRIVE_STRENGTH_10_100UA = 1, /*!< HBN LDO11RT drive strength 1: 10uA to 100uA */ 241 HBN_LDO11RT_DRIVE_STRENGTH_15_150UA = 2, /*!< HBN LDO11RT drive strength 2: 15uA to 150uA */ 242 HBN_LDO11RT_DRIVE_STRENGTH_25_250UA = 3, /*!< HBN LDO11RT drive strength 3: 25uA to 250uA */ 243 } HBN_LDO11RT_DRIVE_STRENGTH_Type; 244 245 /** 246 * @brief HBN level type definition 247 */ 248 typedef enum { 249 HBN_LEVEL_0, /*!< HBN pd_core */ 250 HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */ 251 HBN_LEVEL_2, /*!< HBN pd_aon_hbncore + pd_core */ 252 HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ 253 } HBN_LEVEL_Type; 254 255 /** 256 * @brief HBN BOR configuration type definition 257 */ 258 typedef struct 259 { 260 uint8_t enableBor; /*!< Enable BOR or not */ 261 uint8_t enableBorInt; /*!< Enable BOR interrupt or not */ 262 uint8_t borThreshold; /*!< BOR threshold */ 263 uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */ 264 } HBN_BOR_CFG_Type; 265 266 /** 267 * @brief HBN APP configuration type definition 268 */ 269 typedef struct 270 { 271 uint8_t useXtal32k; /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */ 272 uint32_t sleepTime; /*!< HBN sleep time */ 273 uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */ 274 HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */ 275 spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ 276 uint8_t flashPinCfg; /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */ 277 HBN_LEVEL_Type hbnLevel; /*!< HBN level */ 278 HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ 279 } HBN_APP_CFG_Type; 280 281 /*@} end of group HBN_Public_Types */ 282 283 /** @defgroup HBN_Public_Constants 284 * @{ 285 */ 286 287 /** @defgroup HBN_PIR_LPF_TYPE 288 * @{ 289 */ 290 #define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \ 291 ((type) == HBN_PIR_LPF_DIV2)) 292 293 /** @defgroup HBN_PIR_HPF_TYPE 294 * @{ 295 */ 296 #define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \ 297 ((type) == HBN_PIR_HPF_METHOD1) || \ 298 ((type) == HBN_PIR_HPF_METHOD2)) 299 300 /** @defgroup HBN_BOR_THRES_TYPE 301 * @{ 302 */ 303 #define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \ 304 ((type) == HBN_BOR_THRES_2P4V)) 305 306 /** @defgroup HBN_BOR_MODE_TYPE 307 * @{ 308 */ 309 #define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \ 310 ((type) == HBN_BOR_MODE_POR_RELEVANT)) 311 312 /** @defgroup HBN_32K_CLK_TYPE 313 * @{ 314 */ 315 #define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) || \ 316 ((type) == HBN_32K_XTAL) || \ 317 ((type) == HBN_32K_DIG)) 318 319 /** @defgroup HBN_XCLK_CLK_TYPE 320 * @{ 321 */ 322 #define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \ 323 ((type) == HBN_XCLK_CLK_XTAL)) 324 325 /** @defgroup HBN_ROOT_CLK_TYPE 326 * @{ 327 */ 328 #define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \ 329 ((type) == HBN_ROOT_CLK_XTAL) || \ 330 ((type) == HBN_ROOT_CLK_DLL)) 331 332 /** @defgroup HBN_UART_CLK_TYPE 333 * @{ 334 */ 335 #define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \ 336 ((type) == HBN_UART_CLK_96M)) 337 338 /** @defgroup HBN_RTC_INT_DELAY_TYPE 339 * @{ 340 */ 341 #define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \ 342 ((type) == HBN_RTC_INT_DELAY_0T)) 343 344 /** @defgroup HBN_INT_TYPE 345 * @{ 346 */ 347 #define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO9) || \ 348 ((type) == HBN_INT_GPIO10) || \ 349 ((type) == HBN_INT_GPIO11) || \ 350 ((type) == HBN_INT_GPIO12) || \ 351 ((type) == HBN_INT_GPIO13) || \ 352 ((type) == HBN_INT_RTC) || \ 353 ((type) == HBN_INT_PIR) || \ 354 ((type) == HBN_INT_BOR) || \ 355 ((type) == HBN_INT_ACOMP0) || \ 356 ((type) == HBN_INT_ACOMP1)) 357 358 /** @defgroup HBN_ACOMP_INT_EDGE_TYPE 359 * @{ 360 */ 361 #define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \ 362 ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE)) 363 364 /** @defgroup HBN_RST_EVENT_TYPE 365 * @{ 366 */ 367 #define IS_HBN_RST_EVENT_TYPE(type) (((type) == HBN_RST_EVENT_POR_OUT) || \ 368 ((type) == HBN_RST_EVENT_EXT_RST_N) || \ 369 ((type) == HBN_RST_EVENT_SW_RST) || \ 370 ((type) == HBN_RST_EVENT_PWR_RST_N) || \ 371 ((type) == HBN_RST_EVENT_BOR_OUT)) 372 373 /** @defgroup HBN_GPIO_INT_TRIGGER_TYPE 374 * @{ 375 */ 376 #define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ 377 ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ 378 ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ 379 ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ 380 ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ 381 ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ 382 ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ 383 ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) 384 385 /** @defgroup HBN_OUT0_INT_TYPE 386 * @{ 387 */ 388 #define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO9) || \ 389 ((type) == HBN_OUT0_INT_GPIO10) || \ 390 ((type) == HBN_OUT0_INT_GPIO11) || \ 391 ((type) == HBN_OUT0_INT_GPIO12) || \ 392 ((type) == HBN_OUT0_INT_GPIO13) || \ 393 ((type) == HBN_OUT0_INT_RTC) || \ 394 ((type) == HBN_OUT0_MAX)) 395 396 /** @defgroup HBN_OUT1_INT_TYPE 397 * @{ 398 */ 399 #define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) || \ 400 ((type) == HBN_OUT1_INT_BOR) || \ 401 ((type) == HBN_OUT1_INT_ACOMP0) || \ 402 ((type) == HBN_OUT1_INT_ACOMP1) || \ 403 ((type) == HBN_OUT1_MAX)) 404 405 /** @defgroup HBN_LDO_LEVEL_TYPE 406 * @{ 407 */ 408 #define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \ 409 ((type) == HBN_LDO_LEVEL_0P65V) || \ 410 ((type) == HBN_LDO_LEVEL_0P70V) || \ 411 ((type) == HBN_LDO_LEVEL_0P75V) || \ 412 ((type) == HBN_LDO_LEVEL_0P80V) || \ 413 ((type) == HBN_LDO_LEVEL_0P85V) || \ 414 ((type) == HBN_LDO_LEVEL_0P90V) || \ 415 ((type) == HBN_LDO_LEVEL_0P95V) || \ 416 ((type) == HBN_LDO_LEVEL_1P00V) || \ 417 ((type) == HBN_LDO_LEVEL_1P05V) || \ 418 ((type) == HBN_LDO_LEVEL_1P10V) || \ 419 ((type) == HBN_LDO_LEVEL_1P15V) || \ 420 ((type) == HBN_LDO_LEVEL_1P20V) || \ 421 ((type) == HBN_LDO_LEVEL_1P25V) || \ 422 ((type) == HBN_LDO_LEVEL_1P30V) || \ 423 ((type) == HBN_LDO_LEVEL_1P35V)) 424 425 /** @defgroup HBN_LDO11RT_DRIVE_STRENGTH_TYPE 426 * @{ 427 */ 428 #define IS_HBN_LDO11RT_DRIVE_STRENGTH_TYPE(type) (((type) == HBN_LDO11RT_DRIVE_STRENGTH_5_50UA) || \ 429 ((type) == HBN_LDO11RT_DRIVE_STRENGTH_10_100UA) || \ 430 ((type) == HBN_LDO11RT_DRIVE_STRENGTH_15_150UA) || \ 431 ((type) == HBN_LDO11RT_DRIVE_STRENGTH_25_250UA)) 432 433 /** @defgroup HBN_LEVEL_TYPE 434 * @{ 435 */ 436 #define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \ 437 ((type) == HBN_LEVEL_1) || \ 438 ((type) == HBN_LEVEL_2) || \ 439 ((type) == HBN_LEVEL_3)) 440 441 /*@} end of group HBN_Public_Constants */ 442 443 /** @defgroup HBN_Public_Macros 444 * @{ 445 */ 446 #define HBN_RAM_SIZE (4 * 1024) 447 #define HBN_RTC_COMP_BIT0_39 0x01 448 #define HBN_RTC_COMP_BIT0_23 0x02 449 #define HBN_RTC_COMP_BIT13_39 0x04 450 #define HBN_STATUS_ENTER_FLAG 0x4e424845 451 #define HBN_STATUS_WAKEUP_FLAG 0x4e424857 452 #define HBN_WAKEUP_GPIO_NONE 0x00 453 #define HBN_WAKEUP_GPIO_9 0x01 454 #define HBN_WAKEUP_GPIO_10 0x02 455 #define HBN_WAKEUP_GPIO_11 0x04 456 #define HBN_WAKEUP_GPIO_12 0x08 457 #define HBN_WAKEUP_GPIO_13 0x10 458 #define HBN_WAKEUP_GPIO_ALL 0x1E 459 460 /*@} end of group HBN_Public_Macros */ 461 462 /** @defgroup HBN_Public_Functions 463 * @{ 464 */ 465 /*----------*/ 466 #ifndef BFLB_USE_HAL_DRIVER 467 void HBN_OUT0_IRQHandler(void); 468 void HBN_OUT1_IRQHandler(void); 469 #endif 470 /*----------*/ 471 void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg); 472 void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg); 473 void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); 474 BL_Err_Type HBN_Reset(void); 475 BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv); 476 BL_Err_Type HBN_Disable(void); 477 /*----------*/ 478 BL_Err_Type HBN_PIR_Enable(void); 479 BL_Err_Type HBN_PIR_Disable(void); 480 BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg); 481 BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf); 482 BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf); 483 BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold); 484 uint16_t HBN_Get_PIR_Threshold(void); 485 BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval); 486 uint16_t HBN_Get_PIR_Interval(void); 487 /*----------*/ 488 BL_Sts_Type HBN_Get_BOR_OUT_State(void); 489 BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode); 490 /*----------*/ 491 BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel); 492 BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel); 493 BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel); 494 BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel); 495 BL_Err_Type HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_Type strength); 496 /*----------*/ 497 BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType); 498 BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel); 499 BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk); 500 BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk); 501 /*----------*/ 502 BL_Err_Type HBN_Set_HRAM_slp(void); 503 BL_Err_Type HBN_Set_HRAM_Ret(void); 504 /*----------*/ 505 uint32_t HBN_Get_Status_Flag(void); 506 BL_Err_Type HBN_Set_Status_Flag(uint32_t flag); 507 uint32_t HBN_Get_Wakeup_Addr(void); 508 BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr); 509 /*----------*/ 510 BL_Err_Type HBN_Clear_RTC_Counter(void); 511 BL_Err_Type HBN_Enable_RTC_Counter(void); 512 BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode); 513 BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh); 514 BL_Err_Type HBN_Clear_RTC_INT(void); 515 /*----------*/ 516 BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType); 517 BL_Err_Type HBN_GPIO_INT_Disable(void); 518 BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType); 519 uint8_t HBN_Get_Pin_Wakeup_Mode(void); 520 BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType); 521 BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable); 522 BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg); 523 BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal); 524 /*----------*/ 525 BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); 526 BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge); 527 BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); 528 BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge); 529 /*----------*/ 530 BL_Err_Type HBN_Enable_BOR_IRQ(void); 531 BL_Err_Type HBN_Disable_BOR_IRQ(void); 532 /*----------*/ 533 BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event); 534 BL_Err_Type HBN_Clear_Reset_Event(void); 535 /*----------*/ 536 BL_Err_Type HBN_Out0_IRQHandler_Install(void); 537 BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun); 538 BL_Err_Type HBN_Out1_IRQHandler_Install(void); 539 BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun); 540 /*----------*/ 541 BL_Err_Type HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, 542 uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask); 543 /*----------*/ 544 BL_Err_Type HBN_Power_On_Xtal_32K(void); 545 BL_Err_Type HBN_Power_Off_Xtal_32K(void); 546 BL_Err_Type HBN_Power_On_RC32K(void); 547 BL_Err_Type HBN_Power_Off_RC32K(void); 548 BL_Err_Type HBN_Trim_RC32K(void); 549 BL_Err_Type HBN_Set_Pad_23_28_Pullnone(void); 550 BL_Err_Type HBN_Set_Pad_23_28_Pullup(void); 551 BL_Err_Type HBN_Set_Pad_23_28_Pulldown(void); 552 BL_Err_Type HBN_Set_Pad_23_28_ActiveIE(void); 553 BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg); 554 /*----------*/ 555 void HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); 556 /*----------*/; 557 558 /*@} end of group HBN_Public_Functions */ 559 560 /*@} end of group HBN */ 561 562 /*@} end of group BL702_Peripheral_Driver */ 563 564 #endif /* __BL702_HBN_H__ */ 565