1 /** 2 ****************************************************************************** 3 * @file bl702_pds.h 4 * @version V1.0 5 * @date 6 * @brief This file is the standard driver header file 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __BL702_PDS_H__ 37 #define __BL702_PDS_H__ 38 39 #include "pds_reg.h" 40 #include "bl702_ef_ctrl.h" 41 #include "bl702_aon.h" 42 #include "bl702_hbn.h" 43 #include "bl702_common.h" 44 #include "bflb_sflash.h" 45 46 /** @addtogroup BL702_Peripheral_Driver 47 * @{ 48 */ 49 50 /** @addtogroup PDS 51 * @{ 52 */ 53 54 /** @defgroup PDS_Public_Types 55 * @{ 56 */ 57 58 /** 59 * @brief PDS LDO level type definition 60 */ 61 typedef enum { 62 PDS_LDO_LEVEL_0P60V = 0, /*!< PDS LDO voltage 0.60V */ 63 PDS_LDO_LEVEL_0P65V = 1, /*!< PDS LDO voltage 0.65V */ 64 PDS_LDO_LEVEL_0P70V = 2, /*!< PDS LDO voltage 0.70V */ 65 PDS_LDO_LEVEL_0P75V = 3, /*!< PDS LDO voltage 0.75V */ 66 PDS_LDO_LEVEL_0P80V = 4, /*!< PDS LDO voltage 0.80V */ 67 PDS_LDO_LEVEL_0P85V = 5, /*!< PDS LDO voltage 0.85V */ 68 PDS_LDO_LEVEL_0P90V = 6, /*!< PDS LDO voltage 0.90V */ 69 PDS_LDO_LEVEL_0P95V = 7, /*!< PDS LDO voltage 0.95V */ 70 PDS_LDO_LEVEL_1P00V = 8, /*!< PDS LDO voltage 1.00V */ 71 PDS_LDO_LEVEL_1P05V = 9, /*!< PDS LDO voltage 1.05V */ 72 PDS_LDO_LEVEL_1P10V = 10, /*!< PDS LDO voltage 1.10V */ 73 PDS_LDO_LEVEL_1P15V = 11, /*!< PDS LDO voltage 1.15V */ 74 PDS_LDO_LEVEL_1P20V = 12, /*!< PDS LDO voltage 1.20V */ 75 PDS_LDO_LEVEL_1P25V = 13, /*!< PDS LDO voltage 1.25V */ 76 PDS_LDO_LEVEL_1P30V = 14, /*!< PDS LDO voltage 1.30V */ 77 PDS_LDO_LEVEL_1P35V = 15, /*!< PDS LDO voltage 1.35V */ 78 } PDS_LDO_LEVEL_Type; 79 80 /** 81 * @brief PDS RAM configuration type definition 82 */ 83 typedef struct 84 { 85 uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET1N : 1; /*!< [0] 0~16KB cpu_ram RET1N */ 86 uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET1N : 1; /*!< [1] 16~32KB cpu_ram RET1N */ 87 uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET1N : 1; /*!< [2] 32~48KB cpu_ram RET1N */ 88 uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET1N : 1; /*!< [3] 48~64KB cpu_ram RET1N */ 89 uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET2N : 1; /*!< [4] 0~16KB cpu_ram RET2N */ 90 uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET2N : 1; /*!< [5] 16~32KB cpu_ram RET2N */ 91 uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET2N : 1; /*!< [6] 32~48KB cpu_ram RET2N */ 92 uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET2N : 1; /*!< [7] 48~64KB cpu_ram RET2N */ 93 uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_PGEN : 1; /*!< [8] 0~16KB cpu_ram PGEN */ 94 uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_PGEN : 1; /*!< [9] 16~32KB cpu_ram PGEN */ 95 uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_PGEN : 1; /*!< [10] 32~48KB cpu_ram PGEN */ 96 uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_PGEN : 1; /*!< [11] 48~64KB cpu_ram PGEN */ 97 uint32_t PDS_RAM_CFG_RSV : 20; /*!< [31:12]reserve */ 98 } PDS_RAM_CFG_Type; 99 100 /** 101 * @brief PDS PAD pin configuration type definition 102 */ 103 typedef enum { 104 PDS_PAD_PIN_GPIO_17, /*!< PAD GPIO 17 */ 105 PDS_PAD_PIN_GPIO_18, /*!< PAD GPIO 18 */ 106 PDS_PAD_PIN_GPIO_19, /*!< PAD GPIO 19 */ 107 PDS_PAD_PIN_GPIO_20, /*!< PAD GPIO 20 */ 108 PDS_PAD_PIN_GPIO_21, /*!< PAD GPIO 21 */ 109 PDS_PAD_PIN_GPIO_22, /*!< PAD GPIO 22 */ 110 PDS_PAD_PIN_GPIO_23, /*!< PAD GPIO 23 */ 111 PDS_PAD_PIN_GPIO_24, /*!< PAD GPIO 24 */ 112 PDS_PAD_PIN_GPIO_25, /*!< PAD GPIO 25 */ 113 PDS_PAD_PIN_GPIO_26, /*!< PAD GPIO 26 */ 114 PDS_PAD_PIN_GPIO_27, /*!< PAD GPIO 27 */ 115 PDS_PAD_PIN_GPIO_28, /*!< PAD GPIO 28 */ 116 } PDS_PAD_PIN_Type; 117 118 /** 119 * @brief PDS PAD configuration type definition 120 */ 121 typedef enum { 122 PDS_PAD_CFG_PULL_NONE, /*!< no PD/PU/IE on PAD */ 123 PDS_PAD_CFG_PULL_DOWN, /*!< Pulldown PAD */ 124 PDS_PAD_CFG_PULL_UP, /*!< Pullup PAD */ 125 PDS_PAD_CFG_ACTIVE_IE, /*!< Active IE */ 126 } PDS_PAD_CFG_Type; 127 128 /** 129 * @brief PDS configuration type definition 130 */ 131 typedef struct 132 { 133 uint32_t pdsStart : 1; /*!< [0]PDS Start */ 134 uint32_t sleepForever : 1; /*!< [1]PDS sleep forever */ 135 uint32_t xtalForceOff : 1; /*!< [2]Power off xtal force */ 136 uint32_t saveWifiState : 1; /*!< [3]Save WIFI State Before Enter PDS */ 137 uint32_t dcdc18Off : 1; /*!< [4]power down dcdc18 during PDS */ 138 uint32_t bgSysOff : 1; /*!< [5]power down bg_sys during PDS */ 139 uint32_t gpioIePuPd : 1; /*!< [6]allow PDS Control the GPIO IE/PU/PD at Sleep Mode */ 140 uint32_t puFlash : 1; /*!< [7]turn off Flash Power During PDS */ 141 uint32_t clkOff : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */ 142 uint32_t memStby : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */ 143 uint32_t swPuFlash : 1; /*!< [10]SW Turn on Flash */ 144 uint32_t isolation : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */ 145 uint32_t waitXtalRdy : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */ 146 uint32_t pdsPwrOff : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */ 147 uint32_t xtalOff : 1; /*!< [14]xtal power down during PDS */ 148 uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */ 149 uint32_t pdsRstSocEn : 1; /*!< [16]pds_rst controlled by PDS */ 150 uint32_t pdsRC32mOn : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */ 151 uint32_t pdsLdoVselEn : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */ 152 uint32_t pdsRamLowPowerWithClkEn : 1; /*!< [19]Control SRAM Low Power with CLK (Sync) */ 153 uint32_t reserved20 : 1; /*!< [20]Reserved */ 154 uint32_t cpu0WfiMask : 1; /*!< [21]pds start condition mask np_wfi */ 155 uint32_t ldo11Off : 1; /*!< [22]power down ldo11 during PDS */ 156 uint32_t pdsForceRamClkEn : 1; /*!< [23]Force SRAM CLK Enable */ 157 uint32_t pdsLdoVol : 4; /*!< [27:24]LDO voltage value in PDS mode */ 158 uint32_t pdsCtlRfSel : 2; /*!< [29:28]select the way RF controlled by PDS */ 159 uint32_t pdsCtlPllSel : 2; /*!< [31:30]select the way PLL controlled by PDS */ 160 } PDS_CFG_Type; 161 162 /** 163 * @brief PDS configuration type definition 164 */ 165 typedef struct 166 { 167 uint32_t pdsStart : 1; /*!< [0]PDS Start */ 168 uint32_t sleepForever : 1; /*!< [1]PDS sleep forever */ 169 uint32_t xtalForceOff : 1; /*!< [2]Power off xtal force */ 170 uint32_t saveWifiState : 1; /*!< [3]Save WIFI State Before Enter PDS */ 171 uint32_t dcdc18Off : 1; /*!< [4]power down dcdc18 during PDS */ 172 uint32_t bgSysOff : 1; /*!< [5]power down bg_sys during PDS */ 173 uint32_t gpioIePuPd : 1; /*!< [6]allow PDS Control the GPIO IE/PU/PD at Sleep Mode */ 174 uint32_t puFlash : 1; /*!< [7]turn off Flash Power During PDS */ 175 uint32_t clkOff : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */ 176 uint32_t memStby : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */ 177 uint32_t swPuFlash : 1; /*!< [10]SW Turn on Flash */ 178 uint32_t isolation : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */ 179 uint32_t waitXtalRdy : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */ 180 uint32_t pdsPwrOff : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */ 181 uint32_t xtalOff : 1; /*!< [14]xtal power down during PDS */ 182 uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */ 183 uint32_t pdsRstSocEn : 1; /*!< [16]pds_rst controlled by PDS */ 184 uint32_t pdsRC32mOn : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */ 185 uint32_t pdsLdoVselEn : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */ 186 uint32_t pdsRamLowPowerWithClkEn : 1; /*!< [19]Control SRAM Low Power with CLK (Sync) */ 187 uint32_t reserved20 : 1; /*!< [20]Reserved */ 188 uint32_t cpu0WfiMask : 1; /*!< [21]pds start condition mask np_wfi */ 189 uint32_t ldo11Off : 1; /*!< [22]power down ldo11 during PDS */ 190 uint32_t pdsForceRamClkEn : 1; /*!< [23]Force SRAM CLK Enable */ 191 uint32_t pdsLdoVol : 4; /*!< [27:24]LDO voltage value in PDS mode */ 192 uint32_t pdsCtlRfSel : 2; /*!< [29:28]select the way RF controlled by PDS */ 193 uint32_t pdsCtlPllSel : 2; /*!< [31:30]select the way PLL controlled by PDS */ 194 } PDS_CTL_Type; 195 196 /** 197 * @brief PDS force configuration type definition 198 */ 199 typedef struct 200 { 201 uint32_t forceCpuPwrOff : 1; /*!< [0]manual force NP power off */ 202 uint32_t rsv1 : 1; /*!< [1]reserve */ 203 uint32_t forceBzPwrOff : 1; /*!< [2]manual force BZ power off */ 204 uint32_t forceUsbPwrOff : 1; /*!< [3]manual force USB power off */ 205 uint32_t forceCpuIsoEn : 1; /*!< [4]manual force NP isolation */ 206 uint32_t rsv5 : 1; /*!< [5]reserve */ 207 uint32_t forceBzIsoEn : 1; /*!< [6]manual force BZ isolation */ 208 uint32_t forceUsbIsoEn : 1; /*!< [7]manual force USB isolation */ 209 uint32_t forceCpuPdsRst : 1; /*!< [8]manual force NP pds reset */ 210 uint32_t rsv9 : 1; /*!< [9]reserve */ 211 uint32_t forceBzPdsRst : 1; /*!< [10]manual force BZ pds reset */ 212 uint32_t forceUsbPdsRst : 1; /*!< [11]manual force USB pds reset */ 213 uint32_t forceCpuMemStby : 1; /*!< [12]manual force NP memory sleep */ 214 uint32_t rsv13 : 1; /*!< [13]reserve */ 215 uint32_t forceBzMemStby : 1; /*!< [14]manual force BZ memory sleep */ 216 uint32_t forceUsbMemStby : 1; /*!< [15]manual force USB memory sleep */ 217 uint32_t forceCpuGateClk : 1; /*!< [16]manual force NP clock gated */ 218 uint32_t rsv17 : 1; /*!< [17]reserve */ 219 uint32_t forceBzGateClk : 1; /*!< [18]manual force BZ clock gated */ 220 uint32_t forceUsbGateClk : 1; /*!< [19]manual force USB clock gated */ 221 uint32_t rsv20_31 : 12; /*!< [31:20]reserve */ 222 } PDS_CTL2_Type; 223 224 /** 225 * @brief PDS force configuration type definition 226 */ 227 typedef struct 228 { 229 uint32_t rsv0 : 1; /*!< [0]reserve */ 230 uint32_t forceMiscPwrOff : 1; /*!< [1]manual force MISC pwr_off */ 231 uint32_t forceBlePwrOff : 1; /*!< [2]manual force BZ_BLE pwr_off */ 232 uint32_t rsv3_4 : 2; /*!< [4:3]reserve */ 233 uint32_t forceBleIsoEn : 1; /*!< [5]manual force BZ_BLE iso_en */ 234 uint32_t rsv6 : 1; /*!< [6]reserve */ 235 uint32_t forceMiscPdsRst : 1; /*!< [7]manual force MISC pds_rst */ 236 uint32_t forceBlePdsRst : 1; /*!< [8]manual force BZ_BLE pds_rst */ 237 uint32_t rsv9 : 1; /*!< [9]reserve */ 238 uint32_t forceMiscMemStby : 1; /*!< [10]manual force MISC mem_stby */ 239 uint32_t forceBleMemStby : 1; /*!< [11]manual force BZ_BLE mem_stby */ 240 uint32_t rsv12 : 1; /*!< [12]reserve */ 241 uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */ 242 uint32_t forceBleGateClk : 1; /*!< [14]manual force BZ_BLE gate_clk */ 243 uint32_t rsv15_23 : 9; /*!< [23:15]reserve */ 244 uint32_t CpuIsoEn : 1; /*!< [24]make NP isolated at PDS Sleep state */ 245 uint32_t rsv25_26 : 2; /*!< [26:25]reserve */ 246 uint32_t BzIsoEn : 1; /*!< [27]make BZ isolated at PDS Sleep state */ 247 uint32_t BleIsoEn : 1; /*!< [28]make Ble isolated at PDS Sleep state */ 248 uint32_t UsbIsoEn : 1; /*!< [29]make USB isolated at PDS Sleep state */ 249 uint32_t MiscIsoEn : 1; /*!< [30]make misc isolated at PDS Sleep state */ 250 uint32_t rsv31 : 1; /*!< [31]reserve */ 251 } PDS_CTL3_Type; 252 253 /** 254 * @brief PDS force configuration type definition 255 */ 256 typedef struct 257 { 258 uint32_t cpuPwrOff : 1; /*!< [0] */ 259 uint32_t cpuRst : 1; /*!< [1] */ 260 uint32_t cpuMemStby : 1; /*!< [2] */ 261 uint32_t cpuGateClk : 1; /*!< [3] */ 262 uint32_t rsv4_11 : 8; /*!< [11:4]reserve */ 263 uint32_t BzPwrOff : 1; /*!< [12] */ 264 uint32_t BzRst : 1; /*!< [13] */ 265 uint32_t BzMemStby : 1; /*!< [14] */ 266 uint32_t BzGateClk : 1; /*!< [15] */ 267 uint32_t BlePwrOff : 1; /*!< [16] */ 268 uint32_t BleRst : 1; /*!< [17] */ 269 uint32_t BleMemStby : 1; /*!< [18] */ 270 uint32_t BleGateClk : 1; /*!< [19] */ 271 uint32_t UsbPwrOff : 1; /*!< [20] */ 272 uint32_t UsbRst : 1; /*!< [21] */ 273 uint32_t UsbMemStby : 1; /*!< [22] */ 274 uint32_t UsbGateClk : 1; /*!< [23] */ 275 uint32_t MiscPwrOff : 1; /*!< [24] */ 276 uint32_t MiscRst : 1; /*!< [25] */ 277 uint32_t MiscMemStby : 1; /*!< [26] */ 278 uint32_t MiscGateClk : 1; /*!< [27] */ 279 uint32_t rsv28_29 : 2; /*!< [29:28]reserve */ 280 uint32_t MiscAnaPwrOff : 1; /*!< [30] */ 281 uint32_t MiscDigPwrOff : 1; /*!< [31] */ 282 } PDS_CTL4_Type; 283 284 /** 285 * @brief PDS default level configuration type definition 286 */ 287 typedef struct 288 { 289 PDS_CTL_Type pdsCtl; /*!< PDS_CTL configuration */ 290 PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */ 291 PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */ 292 PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */ 293 } PDS_DEFAULT_LV_CFG_Type; 294 295 /** 296 * @brief PDS interrupt type definition 297 */ 298 typedef enum { 299 PDS_INT_WAKEUP = 0, /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */ 300 PDS_INT_RF_DONE, /*!< PDS RF done interrupt */ 301 PDS_INT_PLL_DONE, /*!< PDS PLL done interrupt */ 302 PDS_INT_PDS_SLEEP_CNT, /*!< wakeup trigger by pds_sleep_cnt=0 */ 303 PDS_INT_HBN_IRQ_OUT0, /*!< wakeup trigger by hbn_irq_out[0] */ 304 PDS_INT_HBN_IRQ_OUT1, /*!< wakeup trigger by hbn_irq_out[1] */ 305 PDS_INT_GPIO_IRQ, /*!< wakeup trigger by gpio_irq */ 306 PDS_INT_IRRX, /*!< wakeup trigger by irrx_int */ 307 PDS_INT_BLE_SLP_IRQ, /*!< wakeup trigger by ble_slp_irq */ 308 PDS_INT_USB_WKUP, /*!< wakeup trigger by usb_wkup */ 309 PDS_INT_KYS_QDEC, /*!< wakeup trigger by kys_int or qdec */ 310 PDS_INT_MAX, /*!< PDS int max number */ 311 } PDS_INT_Type; 312 313 /** 314 * @brief PDS vddcore GPIO interrupt type definition 315 */ 316 typedef enum { 317 PDS_VDDCORE_GPIO_SRC_GPIO_0, /*!< PDS VDDCORE GPIO0 as PDS interrupt source */ 318 PDS_VDDCORE_GPIO_SRC_GPIO_1, /*!< PDS VDDCORE GPIO1 as PDS interrupt source */ 319 PDS_VDDCORE_GPIO_SRC_GPIO_2, /*!< PDS VDDCORE GPIO2 as PDS interrupt source */ 320 PDS_VDDCORE_GPIO_SRC_GPIO_3, /*!< PDS VDDCORE GPIO3 as PDS interrupt source */ 321 PDS_VDDCORE_GPIO_SRC_GPIO_4, /*!< PDS VDDCORE GPIO4 as PDS interrupt source */ 322 PDS_VDDCORE_GPIO_SRC_GPIO_5, /*!< PDS VDDCORE GPIO5 as PDS interrupt source */ 323 PDS_VDDCORE_GPIO_SRC_GPIO_6, /*!< PDS VDDCORE GPIO6 as PDS interrupt source */ 324 PDS_VDDCORE_GPIO_SRC_GPIO_7, /*!< PDS VDDCORE GPIO7 as PDS interrupt source */ 325 } PDS_VDDCORE_GPIO_SRC_Type; 326 327 /** 328 * @brief PDS reset event type definition 329 */ 330 typedef enum { 331 PDS_RST_EVENT_BUS_RST, /*!< hreset_n (Bus Reset) */ 332 PDS_RST_EVENT_HBN_PWR_ON_RST, /*!< pwr_rst_n (hbn power on reset) */ 333 PDS_RST_EVENT_PDS_RST, /*!< pds_rst_n (pds reset) */ 334 PDS_RST_EVENT_MAX, /*!< PDS rst event max number */ 335 } PDS_RST_EVENT_Type; 336 337 /** 338 * @brief PDS PLL status type definition 339 */ 340 typedef enum { 341 PDS_PLL_STS_OFF = 0, /*!< 2'b00 */ 342 PDS_PLL_STS_SFREG = 1, /*!< 2'b01 */ 343 PDS_PLL_STS_PU = 2, /*!< 2'b10 */ 344 PDS_PLL_STS_RDY = 3, /*!< 2'b11 */ 345 } PDS_PLL_STS_Type; 346 347 /** 348 * @brief PDS RF status type definition 349 */ 350 typedef enum { 351 PDS_RF_STS_OFF = 0, /*!< 4'b0000 */ 352 PDS_RF_STS_PU_MBG = 1, /*!< 4'b0001 */ 353 PDS_RF_STS_PU_LDO15RF = 3, /*!< 4'b0011 */ 354 PDS_RF_STS_PU_SFREG = 7, /*!< 4'b0111 */ 355 PDS_RF_STS_BZ_EN_AON = 15, /*!< 4'b1111 */ 356 } PDS_RF_STS_Type; 357 358 /** 359 * @brief PDS status type definition 360 */ 361 typedef enum { 362 PDS_STS_IDLE = 0, /*!< 4'b0000 */ 363 PDS_STS_ECG = 8, /*!< 4'b1000 */ 364 PDS_STS_ERST = 12, /*!< 4'b1100 */ 365 PDS_STS_EISO = 15, /*!< 4'b1111 */ 366 PDS_STS_POFF = 7, /*!< 4'b0111 */ 367 PDS_STS_PRE_BGON = 3, /*!< 4'b0011 */ 368 PDS_STS_PRE_BGON1 = 1, /*!< 4'b0001 */ 369 PDS_STS_BGON = 5, /*!< 4'b0101 */ 370 PDS_STS_CLK_SW_32M = 4, /*!< 4'b0100 */ 371 PDS_STS_PON_DCDC = 6, /*!< 4'b0110 */ 372 PDS_STS_PON_LDO11_MISC = 14, /*!< 4'b1110 */ 373 PDS_STS_PON = 10, /*!< 4'b1010 */ 374 PDS_STS_DISO = 2, /*!< 4'b0010 */ 375 PDS_STS_DCG = 13, /*!< 4'b1101 */ 376 PDS_STS_DRST = 11, /*!< 4'b1011 */ 377 PDS_STS_WAIT_EFUSE = 9, /*!< 4'b1001 */ 378 } PDS_STS_Type; 379 380 /** 381 * @brief PLL XTAL type definition 382 */ 383 typedef enum { 384 PDS_PLL_XTAL_NONE, /*!< XTAL is none */ 385 PDS_PLL_XTAL_32M, /*!< XTAL is 32M */ 386 PDS_PLL_XTAL_RC32M, /*!< XTAL is RC32M */ 387 } PDS_PLL_XTAL_Type; 388 389 /** 390 * @brief PLL output clock type definition 391 */ 392 typedef enum { 393 PDS_PLL_CLK_480M, /*!< PLL output clock:480M */ 394 PDS_PLL_CLK_240M, /*!< PLL output clock:240M */ 395 PDS_PLL_CLK_192M, /*!< PLL output clock:192M */ 396 PDS_PLL_CLK_160M, /*!< PLL output clock:160M */ 397 PDS_PLL_CLK_120M, /*!< PLL output clock:120M */ 398 PDS_PLL_CLK_96M, /*!< PLL output clock:96M */ 399 PDS_PLL_CLK_80M, /*!< PLL output clock:80M */ 400 PDS_PLL_CLK_48M, /*!< PLL output clock:48M */ 401 PDS_PLL_CLK_32M, /*!< PLL output clock:32M */ 402 } PDS_PLL_CLK_Type; 403 404 /** 405 * @brief PDS level 0-7 mode HBN GPIO interrupt trigger type definition 406 */ 407 typedef enum { 408 PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync falling edge trigger */ 409 PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync rising edge trigger */ 410 PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync low level trigger */ 411 PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync high level trigger */ 412 PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async falling edge trigger */ 413 PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async rising edge trigger */ 414 PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async low level trigger */ 415 PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async high level trigger */ 416 } PDS_AON_GPIO_INT_Trigger_Type; 417 418 /** 419 * @brief PDS APP configuration type definition 420 */ 421 typedef struct 422 { 423 uint8_t pdsLevel; /*!< PDS level */ 424 uint8_t turnOffXtal32m; /*!< Wheather turn off XTAL32M */ 425 uint8_t turnOffDll; /*!< Wheather turn off DLL */ 426 uint8_t turnOffRF; /*!< Wheather turn off RF */ 427 uint8_t useXtal32k; /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */ 428 uint8_t pdsAonGpioWakeupSrc; /*!< PDS level 0-7,31 mode aon GPIO Wakeup source(HBN wakeup pin) */ 429 PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0-7,31 mode aon GPIO Triger type(HBN wakeup pin) */ 430 uint8_t powerDownFlash; /*!< Whether power down flash */ 431 uint8_t pdsHoldGpio; /*!< Whether pds hold gpio level */ 432 uint8_t turnOffFlashPad; /*!< Whether turn off flash pad(GPIO17-GPIO22, GPIO23-GPIO28) */ 433 uint8_t flashPinCfg; /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */ 434 uint8_t turnoffPLL; /*!< Whether trun off PLL */ 435 uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ 436 uint8_t flashContRead; /*!< Whether enable flash continue read */ 437 uint32_t sleepTime; /*!< PDS sleep time */ 438 spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ 439 HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ 440 void (*preCbFun)(void); /*!< Pre callback function */ 441 void (*postCbFun)(void); /*!< Post callback function */ 442 } PDS_APP_CFG_Type; 443 444 /** 445 * @brief PDS LDO voltage type definition 446 */ 447 typedef enum { 448 PDS_LDO_VOLTAGE_0P60V, /*!< PDS LDO voltage 0.60V */ 449 PDS_LDO_VOLTAGE_0P65V, /*!< PDS LDO voltage 0.65V */ 450 PDS_LDO_VOLTAGE_0P70V, /*!< PDS LDO voltage 0.70V */ 451 PDS_LDO_VOLTAGE_0P75V, /*!< PDS LDO voltage 0.75V */ 452 PDS_LDO_VOLTAGE_0P80V, /*!< PDS LDO voltage 0.80V */ 453 PDS_LDO_VOLTAGE_0P85V, /*!< PDS LDO voltage 0.85V */ 454 PDS_LDO_VOLTAGE_0P90V, /*!< PDS LDO voltage 0.9V */ 455 PDS_LDO_VOLTAGE_0P95V, /*!< PDS LDO voltage 0.95V */ 456 PDS_LDO_VOLTAGE_1P00V, /*!< PDS LDO voltage 1.0V */ 457 PDS_LDO_VOLTAGE_1P05V, /*!< PDS LDO voltage 1.05V */ 458 PDS_LDO_VOLTAGE_1P10V, /*!< PDS LDO voltage 1.1V */ 459 PDS_LDO_VOLTAGE_1P15V, /*!< PDS LDO voltage 1.15V */ 460 PDS_LDO_VOLTAGE_1P20V, /*!< PDS LDO voltage 1.2V */ 461 PDS_LDO_VOLTAGE_1P25V, /*!< PDS LDO voltage 1.25V */ 462 PDS_LDO_VOLTAGE_1P30V, /*!< PDS LDO voltage 1.3V */ 463 PDS_LDO_VOLTAGE_1P35V, /*!< PDS LDO voltage 1.35V */ 464 } PDS_LDO_VOLTAGE_Type; 465 466 /** 467 * @brief PDS auto power down configuration type definition 468 */ 469 typedef struct 470 { 471 BL_Fun_Type mbgPower; /*!< PDS auto [31] MBG power */ 472 BL_Fun_Type ldo18rfPower; /*!< PDS auto [30] LDO18RF power */ 473 BL_Fun_Type sfregPower; /*!< PDS auto [29] SF_REG power */ 474 BL_Fun_Type pllPower; /*!< PDS auto [28] PLL power */ 475 BL_Fun_Type cpu0Power; /*!< PDS auto [19] NP power */ 476 BL_Fun_Type rc32mPower; /*!< PDS auto [17] RC32M power */ 477 BL_Fun_Type xtalPower; /*!< PDS auto [14] XTAL power */ 478 BL_Fun_Type allPower; /*!< PDS auto [13] all power */ 479 BL_Fun_Type isoPower; /*!< PDS auto [11] ISO power */ 480 BL_Fun_Type bzPower; /*!< PDS auto [10] BZ power */ 481 BL_Fun_Type sramDisStanby; /*!< PDS auto [9] SRAM memory stanby disable */ 482 BL_Fun_Type cgPower; /*!< PDS auto [8] CG power */ 483 BL_Fun_Type cpu1Power; /*!< PDS auto [7] AP power */ 484 BL_Fun_Type usbPower; /*!< PDS auto [3] USB power */ 485 } PDS_AUTO_POWER_DOWN_CFG_Type; 486 487 /** 488 * @brief PDS auto configuration type definition 489 */ 490 typedef struct 491 { 492 PDS_LDO_VOLTAGE_Type vddcoreVol; /*!< PDS auto [27:24] VDDCORE voltage, reference 0x4001F80C[27:24], recommended 0xA */ 493 BL_Fun_Type vddcoreVolEn; /*!< PDS auto [18] VDDCORE voltage enable bit */ 494 BL_Fun_Type cpu0NotNeedWFI; /*!< PDS auto [21] NP not need WFI to get in PDS mode */ 495 BL_Fun_Type cpu1NotNeedWFI; /*!< PDS auto [20] AP not need WFI to get in PDS mode */ 496 BL_Fun_Type busReset; /*!< PDS auto [16] bus reset bit, reset after wake up from PDS mode */ 497 BL_Fun_Type disIrqWakeUp; /*!< PDS auto [15] disable IRQ request to wake up from PDS mode, except PDS counter IRQ */ 498 BL_Fun_Type powerOffXtalForever; /*!< PDS auto [2] power off xtal after get in PDS mode, and never power on xtal after wake up */ 499 BL_Fun_Type sleepForever; /*!< PDS auto [1] sleep forever after get in PDS mode, need reset system to restart */ 500 } PDS_AUTO_NORMAL_CFG_Type; 501 502 /** 503 * @brief PDS force type definition 504 */ 505 typedef enum { 506 PDS_FORCE_NP, /*!< PDS force NP */ 507 PDS_FORCE_RSV, /*!< rsv */ 508 PDS_FORCE_BZ, /*!< PDS force BZ */ 509 PDS_FORCE_USB, /*!< PDS force USB */ 510 } PDS_FORCE_Type; 511 512 /** 513 * @brief PDS force type definition 514 */ 515 typedef enum { 516 AUDIO_PLL_12288000_HZ, /*!< PDS AUDIO PLL SET AS 12.288MHZ */ 517 AUDIO_PLL_11289600_HZ, /*!< PDS AUDIO PLL SET AS 11.2896HZ */ 518 AUDIO_PLL_5644800_HZ, /*!< PDS AUDIO PLL SET AS 2.822400HZ */ 519 AUDIO_PLL_24576000_HZ, /*!< PDS AUDIO PLL SET AS 24.576000MHZ */ 520 AUDIO_PLL_24000000_HZ, /*!< PDS AUDIO PLL SET AS 24.000000MHZ */ 521 AUDIO_PLL_50000000_HZ, /*!< PDS AUDIO PLL SET AS 50.000000MHZ */ 522 } PDS_AUDIO_PLL_Type; 523 524 /*@} end of group PDS_Public_Types */ 525 526 /** @defgroup PDS_Public_Constants 527 * @{ 528 */ 529 530 /** @defgroup PDS_LDO_LEVEL_TYPE 531 * @{ 532 */ 533 #define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P60V) || \ 534 ((type) == PDS_LDO_LEVEL_0P65V) || \ 535 ((type) == PDS_LDO_LEVEL_0P70V) || \ 536 ((type) == PDS_LDO_LEVEL_0P75V) || \ 537 ((type) == PDS_LDO_LEVEL_0P80V) || \ 538 ((type) == PDS_LDO_LEVEL_0P85V) || \ 539 ((type) == PDS_LDO_LEVEL_0P90V) || \ 540 ((type) == PDS_LDO_LEVEL_0P95V) || \ 541 ((type) == PDS_LDO_LEVEL_1P00V) || \ 542 ((type) == PDS_LDO_LEVEL_1P05V) || \ 543 ((type) == PDS_LDO_LEVEL_1P10V) || \ 544 ((type) == PDS_LDO_LEVEL_1P15V) || \ 545 ((type) == PDS_LDO_LEVEL_1P20V) || \ 546 ((type) == PDS_LDO_LEVEL_1P25V) || \ 547 ((type) == PDS_LDO_LEVEL_1P30V) || \ 548 ((type) == PDS_LDO_LEVEL_1P35V)) 549 550 /** @defgroup PDS_PAD_PIN_TYPE 551 * @{ 552 */ 553 #define IS_PDS_PAD_PIN_TYPE(type) (((type) == PDS_PAD_PIN_GPIO_17) || \ 554 ((type) == PDS_PAD_PIN_GPIO_18) || \ 555 ((type) == PDS_PAD_PIN_GPIO_19) || \ 556 ((type) == PDS_PAD_PIN_GPIO_20) || \ 557 ((type) == PDS_PAD_PIN_GPIO_21) || \ 558 ((type) == PDS_PAD_PIN_GPIO_22) || \ 559 ((type) == PDS_PAD_PIN_GPIO_23) || \ 560 ((type) == PDS_PAD_PIN_GPIO_24) || \ 561 ((type) == PDS_PAD_PIN_GPIO_25) || \ 562 ((type) == PDS_PAD_PIN_GPIO_26) || \ 563 ((type) == PDS_PAD_PIN_GPIO_27) || \ 564 ((type) == PDS_PAD_PIN_GPIO_28)) 565 566 /** @defgroup PDS_PAD_CFG_TYPE 567 * @{ 568 */ 569 #define IS_PDS_PAD_CFG_TYPE(type) (((type) == PDS_PAD_CFG_PULL_NONE) || \ 570 ((type) == PDS_PAD_CFG_PULL_DOWN) || \ 571 ((type) == PDS_PAD_CFG_PULL_UP) || \ 572 ((type) == PDS_PAD_CFG_ACTIVE_IE)) 573 574 /** @defgroup PDS_INT_TYPE 575 * @{ 576 */ 577 #define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) || \ 578 ((type) == PDS_INT_RF_DONE) || \ 579 ((type) == PDS_INT_PLL_DONE) || \ 580 ((type) == PDS_INT_PDS_SLEEP_CNT) || \ 581 ((type) == PDS_INT_HBN_IRQ_OUT0) || \ 582 ((type) == PDS_INT_HBN_IRQ_OUT1) || \ 583 ((type) == PDS_INT_GPIO_IRQ) || \ 584 ((type) == PDS_INT_IRRX) || \ 585 ((type) == PDS_INT_BLE_SLP_IRQ) || \ 586 ((type) == PDS_INT_USB_WKUP) || \ 587 ((type) == PDS_INT_KYS_QDEC) || \ 588 ((type) == PDS_INT_MAX)) 589 590 /** @defgroup PDS_VDDCORE_GPIO_SRC_TYPE 591 * @{ 592 */ 593 #define IS_PDS_VDDCORE_GPIO_SRC_TYPE(type) (((type) == PDS_VDDCORE_GPIO_SRC_GPIO_0) || \ 594 ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_1) || \ 595 ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_2) || \ 596 ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_3) || \ 597 ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_4) || \ 598 ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_5) || \ 599 ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_6) || \ 600 ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_7)) 601 602 /** @defgroup PDS_RST_EVENT_TYPE 603 * @{ 604 */ 605 #define IS_PDS_RST_EVENT_TYPE(type) (((type) == PDS_RST_EVENT_BUS_RST) || \ 606 ((type) == PDS_RST_EVENT_HBN_PWR_ON_RST) || \ 607 ((type) == PDS_RST_EVENT_PDS_RST) || \ 608 ((type) == PDS_RST_EVENT_MAX)) 609 610 /** @defgroup PDS_PLL_STS_TYPE 611 * @{ 612 */ 613 #define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) || \ 614 ((type) == PDS_PLL_STS_SFREG) || \ 615 ((type) == PDS_PLL_STS_PU) || \ 616 ((type) == PDS_PLL_STS_RDY)) 617 618 /** @defgroup PDS_RF_STS_TYPE 619 * @{ 620 */ 621 #define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) || \ 622 ((type) == PDS_RF_STS_PU_MBG) || \ 623 ((type) == PDS_RF_STS_PU_LDO15RF) || \ 624 ((type) == PDS_RF_STS_PU_SFREG) || \ 625 ((type) == PDS_RF_STS_BZ_EN_AON)) 626 627 /** @defgroup PDS_STS_TYPE 628 * @{ 629 */ 630 #define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) || \ 631 ((type) == PDS_STS_ECG) || \ 632 ((type) == PDS_STS_ERST) || \ 633 ((type) == PDS_STS_EISO) || \ 634 ((type) == PDS_STS_POFF) || \ 635 ((type) == PDS_STS_PRE_BGON) || \ 636 ((type) == PDS_STS_PRE_BGON1) || \ 637 ((type) == PDS_STS_BGON) || \ 638 ((type) == PDS_STS_CLK_SW_32M) || \ 639 ((type) == PDS_STS_PON_DCDC) || \ 640 ((type) == PDS_STS_PON_LDO11_MISC) || \ 641 ((type) == PDS_STS_PON) || \ 642 ((type) == PDS_STS_DISO) || \ 643 ((type) == PDS_STS_DCG) || \ 644 ((type) == PDS_STS_DRST) || \ 645 ((type) == PDS_STS_WAIT_EFUSE)) 646 647 /** @defgroup PDS_PLL_XTAL_TYPE 648 * @{ 649 */ 650 #define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) || \ 651 ((type) == PDS_PLL_XTAL_32M) || \ 652 ((type) == PDS_PLL_XTAL_RC32M)) 653 654 /** @defgroup PDS_PLL_CLK_TYPE 655 * @{ 656 */ 657 #define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \ 658 ((type) == PDS_PLL_CLK_240M) || \ 659 ((type) == PDS_PLL_CLK_192M) || \ 660 ((type) == PDS_PLL_CLK_160M) || \ 661 ((type) == PDS_PLL_CLK_120M) || \ 662 ((type) == PDS_PLL_CLK_96M) || \ 663 ((type) == PDS_PLL_CLK_80M) || \ 664 ((type) == PDS_PLL_CLK_48M) || \ 665 ((type) == PDS_PLL_CLK_32M)) 666 667 /** @defgroup PDS_AON_GPIO_INT_TRIGGER_TYPE 668 * @{ 669 */ 670 #define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ 671 ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ 672 ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ 673 ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ 674 ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ 675 ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ 676 ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ 677 ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) 678 679 /** @defgroup PDS_LDO_VOLTAGE_TYPE 680 * @{ 681 */ 682 #define IS_PDS_LDO_VOLTAGE_TYPE(type) (((type) == PDS_LDO_VOLTAGE_0P60V) || \ 683 ((type) == PDS_LDO_VOLTAGE_0P65V) || \ 684 ((type) == PDS_LDO_VOLTAGE_0P70V) || \ 685 ((type) == PDS_LDO_VOLTAGE_0P75V) || \ 686 ((type) == PDS_LDO_VOLTAGE_0P80V) || \ 687 ((type) == PDS_LDO_VOLTAGE_0P85V) || \ 688 ((type) == PDS_LDO_VOLTAGE_0P90V) || \ 689 ((type) == PDS_LDO_VOLTAGE_0P95V) || \ 690 ((type) == PDS_LDO_VOLTAGE_1P00V) || \ 691 ((type) == PDS_LDO_VOLTAGE_1P05V) || \ 692 ((type) == PDS_LDO_VOLTAGE_1P10V) || \ 693 ((type) == PDS_LDO_VOLTAGE_1P15V) || \ 694 ((type) == PDS_LDO_VOLTAGE_1P20V) || \ 695 ((type) == PDS_LDO_VOLTAGE_1P25V) || \ 696 ((type) == PDS_LDO_VOLTAGE_1P30V) || \ 697 ((type) == PDS_LDO_VOLTAGE_1P35V)) 698 699 /** @defgroup PDS_FORCE_TYPE 700 * @{ 701 */ 702 #define IS_PDS_FORCE_TYPE(type) (((type) == PDS_FORCE_NP) || \ 703 ((type) == PDS_FORCE_RSV) || \ 704 ((type) == PDS_FORCE_BZ) || \ 705 ((type) == PDS_FORCE_USB)) 706 707 /** @defgroup PDS_AUDIO_PLL_TYPE 708 * @{ 709 */ 710 #define IS_PDS_AUDIO_PLL_TYPE(type) (((type) == AUDIO_PLL_12288000_HZ) || \ 711 ((type) == AUDIO_PLL_11289600_HZ) || \ 712 ((type) == AUDIO_PLL_5644800_HZ) || \ 713 ((type) == AUDIO_PLL_24576000_HZ) || \ 714 ((type) == AUDIO_PLL_24000000_HZ) || \ 715 ((type) == AUDIO_PLL_50000000_HZ)) 716 717 /*@} end of group PDS_Public_Constants */ 718 719 /** @defgroup PDS_Public_Macros 720 * @{ 721 */ 722 #define PDS_LDO_MIN_PU_CNT (25) /* LDO need 25 cycles to power up */ 723 #define PDS_WARMUP_CNT (38) /* LDO hw warmup compensation latency cycles */ 724 #define PDS_WARMUP_LATENCY_CNT (38) /* LDO hw warmup compensation latency cycles */ 725 #define PDS_FORCE_PWR_OFF_OFFSET (0) 726 #define PDS_FORCE_ISO_EN_OFFSET (4) 727 #define PDS_FORCE_PDS_RST_OFFSET (8) 728 #define PDS_FORCE_MEM_STBY_OFFSET (12) 729 #define PDS_FORCE_GATE_CLK_OFFSET (16) 730 #define PDS_INT_MASK_BIT_OFFSET (8) 731 #define PDS_AON_WAKEUP_GPIO_NONE (0x00) 732 #define PDS_AON_WAKEUP_GPIO_9 (0x01) 733 #define PDS_AON_WAKEUP_GPIO_10 (0x02) 734 #define PDS_AON_WAKEUP_GPIO_11 (0x04) 735 #define PDS_AON_WAKEUP_GPIO_12 (0x08) 736 #define PDS_AON_WAKEUP_GPIO_13 (0x10) 737 #define PDS_AON_WAKEUP_GPIO_ALL (0x1E) 738 739 /*@} end of group PDS_Public_Macros */ 740 741 /** @defgroup PDS_Public_Functions 742 * @{ 743 */ 744 #ifndef BFLB_USE_HAL_DRIVER 745 void PDS_WAKEUP_IRQHandler(void); 746 #endif 747 /*----------*/ 748 BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg); 749 BL_Err_Type PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin, PDS_PAD_CFG_Type cfg); 750 /*----------*/ 751 BL_Err_Type PDS_App_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt); 752 BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3); 753 BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt); 754 /*----------*/ 755 BL_Err_Type PDS_IntEn(PDS_INT_Type intType, BL_Fun_Type enable); 756 BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask); 757 BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType); 758 BL_Err_Type PDS_IntClear(void); 759 PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void); 760 PDS_RF_STS_Type PDS_Get_PdsRfStstus(void); 761 PDS_STS_Type PDS_Get_PdsStstus(void); 762 /*----------*/ 763 BL_Err_Type PDS_Clear_Reset_Event(void); 764 BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event); 765 /*----------*/ 766 BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src, 767 PDS_AON_GPIO_INT_Trigger_Type mode); 768 BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask); 769 BL_Sts_Type PDS_Get_Vddcore_GPIO_IntStatus(void); 770 BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void); 771 /*----------*/ 772 BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void); 773 BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun); 774 /*----------*/ 775 BL_Err_Type PDS_Trim_RC32M(void); 776 BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void); 777 BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void); 778 BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType); 779 BL_Err_Type PDS_Enable_PLL_All_Clks(void); 780 BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk); 781 BL_Err_Type PDS_Disable_PLL_All_Clks(void); 782 BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk); 783 BL_Err_Type PDS_Power_Off_PLL(void); 784 BL_Err_Type PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq); 785 /*----------*/ 786 void PDS_Reset(void); 787 void PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt); 788 void PDS_Auto_Time_Config(uint32_t sleepDuration); 789 void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable); 790 void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain); 791 void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain); 792 /*----------*/ 793 BL_Err_Type PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel); 794 /*----------*/ 795 796 /*@} end of group PDS_Public_Functions */ 797 798 /*@} end of group PDS */ 799 800 /*@} end of group BL702_Peripheral_Driver */ 801 802 #endif /* __BL702_PDS_H__ */ 803