1 /**
2 ******************************************************************************
3 * @file bl702_sf_cfg_ext.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl702_glb.h"
38 #include "bflb_sf_cfg.h"
39 #include "bl702_sf_cfg_ext.h"
40 #include "bflb_xip_sflash.h"
41 #include "bl702_romdriver.h"
42
43 /** @addtogroup BL702_Peripheral_Driver
44 * @{
45 */
46
47 /** @addtogroup SF_CFG_EXT
48 * @{
49 */
50
51 /** @defgroup SF_CFG_EXT_Private_Macros
52 * @{
53 */
54 #define BFLB_FLASH_CFG_MAGIC "FCFG"
55
56 /*@} end of group SF_CFG_EXT_Private_Macros */
57
58 /** @defgroup SF_CFG_EXT_Private_Types
59 * @{
60 */
61 typedef struct
62 {
63 uint32_t jedec_id;
64 char *name;
65 const spi_flash_cfg_type *cfg;
66 } flash_info_t;
67
68 /*@} end of group SF_CFG_EXT_Private_Types */
69
70 /** @defgroup SF_CFG_EXT_Private_Variables
71 * @{
72 */
73
74 static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_gd_md_40d = {
75 .reset_c_read_cmd = 0xff,
76 .reset_c_read_cmd_size = 3,
77 .mid = 0x51,
78
79 .de_burst_wrap_cmd = 0x77,
80 .de_burst_wrap_cmd_dmy_clk = 0x3,
81 .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
82 .de_burst_wrap_data = 0xF0,
83
84 /*reg*/
85 .write_enable_cmd = 0x06,
86 .wr_enable_index = 0x00,
87 .wr_enable_bit = 0x01,
88 .wr_enable_read_reg_len = 0x01,
89
90 .qe_index = 1,
91 .qe_bit = 0x01,
92 .qe_write_reg_len = 0x02,
93 .qe_read_reg_len = 0x1,
94
95 .busy_index = 0,
96 .busy_bit = 0x00,
97 .busy_read_reg_len = 0x1,
98 .release_powerdown = 0xab,
99
100 .read_reg_cmd[0] = 0x05,
101 .read_reg_cmd[1] = 0x35,
102 .write_reg_cmd[0] = 0x01,
103 .write_reg_cmd[1] = 0x01,
104
105 .fast_read_qio_cmd = 0xeb,
106 .fr_qio_dmy_clk = 16 / 8,
107 .c_read_support = 0,
108 .c_read_mode = 0xA0,
109
110 .burst_wrap_cmd = 0x77,
111 .burst_wrap_cmd_dmy_clk = 0x3,
112 .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
113 .burst_wrap_data = 0x40,
114 /*erase*/
115 .chip_erase_cmd = 0xc7,
116 .sector_erase_cmd = 0x20,
117 .blk32_erase_cmd = 0x52,
118 .blk64_erase_cmd = 0xd8,
119 /*write*/
120 .page_program_cmd = 0x02,
121 .qpage_program_cmd = 0x32,
122 .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
123
124 .io_mode = 0x11,
125 .clk_delay = 1,
126 .clk_invert = 0x3f,
127
128 .reset_en_cmd = 0x66,
129 .reset_cmd = 0x99,
130 .c_rexit = 0xff,
131 .wr_enable_write_reg_len = 0x00,
132
133 /*id*/
134 .jedec_id_cmd = 0x9f,
135 .jedec_id_cmd_dmy_clk = 0,
136 .qpi_jedec_id_cmd = 0x9f,
137 .qpi_jedec_id_cmd_dmy_clk = 0x00,
138 .sector_size = 4,
139 .page_size = 256,
140
141 /*read*/
142 .fast_read_cmd = 0x0b,
143 .fr_dmy_clk = 8 / 8,
144 .qpi_fast_read_cmd = 0x0b,
145 .qpi_fr_dmy_clk = 8 / 8,
146 .fast_read_do_cmd = 0x3b,
147 .fr_do_dmy_clk = 8 / 8,
148 .fast_read_dio_cmd = 0xbb,
149 .fr_dio_dmy_clk = 0,
150 .fast_read_qo_cmd = 0x6b,
151 .fr_qo_dmy_clk = 8 / 8,
152
153 .qpi_fast_read_qio_cmd = 0xeb,
154 .qpi_fr_qio_dmy_clk = 16 / 8,
155 .qpi_page_program_cmd = 0x02,
156 .write_vreg_enable_cmd = 0x50,
157
158 /* qpi mode */
159 .enter_qpi = 0x38,
160 .exit_qpi = 0xff,
161
162 /*AC*/
163 .time_e_sector = 300,
164 .time_e_32k = 1200,
165 .time_e_64k = 1200,
166 .time_page_pgm = 5,
167 .time_ce = 20 * 1000,
168 .pd_delay = 20,
169 .qe_data = 0,
170 };
171
172 static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_mx_kh25 = {
173 .reset_c_read_cmd = 0xff,
174 .reset_c_read_cmd_size = 3,
175 .mid = 0xc2,
176
177 .de_burst_wrap_cmd = 0x77,
178 .de_burst_wrap_cmd_dmy_clk = 0x3,
179 .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
180 .de_burst_wrap_data = 0xF0,
181
182 /*reg*/
183 .write_enable_cmd = 0x06,
184 .wr_enable_index = 0x00,
185 .wr_enable_bit = 0x01,
186 .wr_enable_read_reg_len = 0x01,
187
188 .qe_index = 1,
189 .qe_bit = 0x01,
190 .qe_write_reg_len = 0x02,
191 .qe_read_reg_len = 0x1,
192
193 .busy_index = 0,
194 .busy_bit = 0x00,
195 .busy_read_reg_len = 0x1,
196 .release_powerdown = 0xab,
197
198 .read_reg_cmd[0] = 0x05,
199 .read_reg_cmd[1] = 0x00,
200 .write_reg_cmd[0] = 0x01,
201 .write_reg_cmd[1] = 0x00,
202
203 .fast_read_qio_cmd = 0xeb,
204 .fr_qio_dmy_clk = 16 / 8,
205 .c_read_support = 0,
206 .c_read_mode = 0x20,
207
208 .burst_wrap_cmd = 0x77,
209 .burst_wrap_cmd_dmy_clk = 0x3,
210 .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
211 .burst_wrap_data = 0x40,
212 /*erase*/
213 .chip_erase_cmd = 0xc7,
214 .sector_erase_cmd = 0x20,
215 .blk32_erase_cmd = 0x52,
216 .blk64_erase_cmd = 0xd8,
217 /*write*/
218 .page_program_cmd = 0x02,
219 .qpage_program_cmd = 0x32,
220 .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
221
222 .io_mode = 0x11,
223 .clk_delay = 1,
224 .clk_invert = 0x01,
225
226 .reset_en_cmd = 0x66,
227 .reset_cmd = 0x99,
228 .c_rexit = 0xff,
229 .wr_enable_write_reg_len = 0x00,
230
231 /*id*/
232 .jedec_id_cmd = 0x9f,
233 .jedec_id_cmd_dmy_clk = 0,
234 .qpi_jedec_id_cmd = 0x9f,
235 .qpi_jedec_id_cmd_dmy_clk = 0x00,
236 .sector_size = 4,
237 .page_size = 256,
238
239 /*read*/
240 .fast_read_cmd = 0x0b,
241 .fr_dmy_clk = 8 / 8,
242 .qpi_fast_read_cmd = 0x0b,
243 .qpi_fr_dmy_clk = 8 / 8,
244 .fast_read_do_cmd = 0x3b,
245 .fr_do_dmy_clk = 8 / 8,
246 .fast_read_dio_cmd = 0xbb,
247 .fr_dio_dmy_clk = 0,
248 .fast_read_qo_cmd = 0x6b,
249 .fr_qo_dmy_clk = 8 / 8,
250
251 .qpi_fast_read_qio_cmd = 0xeb,
252 .qpi_fr_qio_dmy_clk = 16 / 8,
253 .qpi_page_program_cmd = 0x02,
254 .write_vreg_enable_cmd = 0x50,
255
256 /* qpi mode */
257 .enter_qpi = 0x38,
258 .exit_qpi = 0xff,
259
260 /*AC*/
261 .time_e_sector = 300,
262 .time_e_32k = 1200,
263 .time_e_64k = 1200,
264 .time_page_pgm = 5,
265 .time_ce = 33000,
266 .pd_delay = 20,
267 .qe_data = 0,
268 };
269
270 static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_fm_q80 = {
271 .reset_c_read_cmd = 0xff,
272 .reset_c_read_cmd_size = 3,
273 .mid = 0xc8,
274
275 .de_burst_wrap_cmd = 0x77,
276 .de_burst_wrap_cmd_dmy_clk = 0x3,
277 .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
278 .de_burst_wrap_data = 0xF0,
279
280 /*reg*/
281 .write_enable_cmd = 0x06,
282 .wr_enable_index = 0x00,
283 .wr_enable_bit = 0x01,
284 .wr_enable_read_reg_len = 0x01,
285
286 .qe_index = 1,
287 .qe_bit = 0x01,
288 .qe_write_reg_len = 0x02,
289 .qe_read_reg_len = 0x1,
290
291 .busy_index = 0,
292 .busy_bit = 0x00,
293 .busy_read_reg_len = 0x1,
294 .release_powerdown = 0xab,
295
296 .read_reg_cmd[0] = 0x05,
297 .read_reg_cmd[1] = 0x35,
298 .write_reg_cmd[0] = 0x01,
299 .write_reg_cmd[1] = 0x01,
300
301 .fast_read_qio_cmd = 0xeb,
302 .fr_qio_dmy_clk = 16 / 8,
303 .c_read_support = 1,
304 .c_read_mode = 0xA0,
305
306 .burst_wrap_cmd = 0x77,
307 .burst_wrap_cmd_dmy_clk = 0x3,
308 .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
309 .burst_wrap_data = 0x40,
310 /*erase*/
311 .chip_erase_cmd = 0xc7,
312 .sector_erase_cmd = 0x20,
313 .blk32_erase_cmd = 0x52,
314 .blk64_erase_cmd = 0xd8,
315 /*write*/
316 .page_program_cmd = 0x02,
317 .qpage_program_cmd = 0x32,
318 .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
319
320 .io_mode = SF_CTRL_QIO_MODE,
321 .clk_delay = 1,
322 .clk_invert = 0x01,
323
324 .reset_en_cmd = 0x66,
325 .reset_cmd = 0x99,
326 .c_rexit = 0xff,
327 .wr_enable_write_reg_len = 0x00,
328
329 /*id*/
330 .jedec_id_cmd = 0x9f,
331 .jedec_id_cmd_dmy_clk = 0,
332 .qpi_jedec_id_cmd = 0x9f,
333 .qpi_jedec_id_cmd_dmy_clk = 0x00,
334 .sector_size = 4,
335 .page_size = 256,
336
337 /*read*/
338 .fast_read_cmd = 0x0b,
339 .fr_dmy_clk = 8 / 8,
340 .qpi_fast_read_cmd = 0x0b,
341 .qpi_fr_dmy_clk = 8 / 8,
342 .fast_read_do_cmd = 0x3b,
343 .fr_do_dmy_clk = 8 / 8,
344 .fast_read_dio_cmd = 0xbb,
345 .fr_dio_dmy_clk = 0,
346 .fast_read_qo_cmd = 0x6b,
347 .fr_qo_dmy_clk = 8 / 8,
348
349 .qpi_fast_read_qio_cmd = 0xeb,
350 .qpi_fr_qio_dmy_clk = 16 / 8,
351 .qpi_page_program_cmd = 0x02,
352 .write_vreg_enable_cmd = 0x50,
353
354 /* qpi mode */
355 .enter_qpi = 0x38,
356 .exit_qpi = 0xff,
357
358 /*AC*/
359 .time_e_sector = 300,
360 .time_e_32k = 1200,
361 .time_e_64k = 1200,
362 .time_page_pgm = 5,
363 .time_ce = 33000,
364 .pd_delay = 20,
365 .qe_data = 0,
366 };
367
368 static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_winb_16jv = {
369 .reset_c_read_cmd = 0xff,
370 .reset_c_read_cmd_size = 3,
371 .mid = 0xef,
372
373 .de_burst_wrap_cmd = 0x77,
374 .de_burst_wrap_cmd_dmy_clk = 0x3,
375 .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
376 .de_burst_wrap_data = 0xF0,
377
378 /*reg*/
379 .write_enable_cmd = 0x06,
380 .wr_enable_index = 0x00,
381 .wr_enable_bit = 0x01,
382 .wr_enable_read_reg_len = 0x01,
383
384 .qe_index = 1,
385 .qe_bit = 0x01,
386 .qe_write_reg_len = 0x01,
387 .qe_read_reg_len = 0x1,
388
389 .busy_index = 0,
390 .busy_bit = 0x00,
391 .busy_read_reg_len = 0x1,
392 .release_powerdown = 0xab,
393
394 .read_reg_cmd[0] = 0x05,
395 .read_reg_cmd[1] = 0x35,
396 .write_reg_cmd[0] = 0x01,
397 .write_reg_cmd[1] = 0x31,
398
399 .fast_read_qio_cmd = 0xeb,
400 .fr_qio_dmy_clk = 16 / 8,
401 .c_read_support = 1,
402 .c_read_mode = 0x20,
403
404 .burst_wrap_cmd = 0x77,
405 .burst_wrap_cmd_dmy_clk = 0x3,
406 .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
407 .burst_wrap_data = 0x40,
408 /*erase*/
409 .chip_erase_cmd = 0xc7,
410 .sector_erase_cmd = 0x20,
411 .blk32_erase_cmd = 0x52,
412 .blk64_erase_cmd = 0xd8,
413 /*write*/
414 .page_program_cmd = 0x02,
415 .qpage_program_cmd = 0x32,
416 .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
417
418 .io_mode = SF_CTRL_QIO_MODE,
419 .clk_delay = 1,
420 .clk_invert = 0x01,
421
422 .reset_en_cmd = 0x66,
423 .reset_cmd = 0x99,
424 .c_rexit = 0xff,
425 .wr_enable_write_reg_len = 0x00,
426
427 /*id*/
428 .jedec_id_cmd = 0x9f,
429 .jedec_id_cmd_dmy_clk = 0,
430 .qpi_jedec_id_cmd = 0x9f,
431 .qpi_jedec_id_cmd_dmy_clk = 0x00,
432 .sector_size = 4,
433 .page_size = 256,
434
435 /*read*/
436 .fast_read_cmd = 0x0b,
437 .fr_dmy_clk = 8 / 8,
438 .qpi_fast_read_cmd = 0x0b,
439 .qpi_fr_dmy_clk = 8 / 8,
440 .fast_read_do_cmd = 0x3b,
441 .fr_do_dmy_clk = 8 / 8,
442 .fast_read_dio_cmd = 0xbb,
443 .fr_dio_dmy_clk = 0,
444 .fast_read_qo_cmd = 0x6b,
445 .fr_qo_dmy_clk = 8 / 8,
446
447 .qpi_fast_read_qio_cmd = 0xeb,
448 .qpi_fr_qio_dmy_clk = 16 / 8,
449 .qpi_page_program_cmd = 0x02,
450 .write_vreg_enable_cmd = 0x50,
451
452 /* qpi mode */
453 .enter_qpi = 0x38,
454 .exit_qpi = 0xff,
455
456 /*AC*/
457 .time_e_sector = 300,
458 .time_e_32k = 1600,
459 .time_e_64k = 1200,
460 .time_page_pgm = 5,
461 .time_ce = 33 * 1000,
462 .pd_delay = 20,
463 .qe_data = 0,
464 };
465
466 static const ATTR_TCM_CONST_SECTION flash_info_t flash_infos[] = {
467 {
468 .jedec_id = 0x134051,
469 .name = "GD_MD04D_04_33",
470 .cfg = &flashcfg_gd_md_40d,
471 },
472 {
473 .jedec_id = 0x1320c2,
474 .name = "MX_KH40_04_33",
475 .cfg = &flashcfg_mx_kh25,
476 },
477 {
478 .jedec_id = 0x1420c2,
479 .name = "MX_KH80_08_33",
480 .cfg = &flashcfg_mx_kh25,
481 },
482 {
483 .jedec_id = 0x1520c2,
484 .name = "MX_KH16_16_33",
485 .cfg = &flashcfg_mx_kh25,
486 },
487 {
488 .jedec_id = 0x1440A1,
489 .name = "FM_25Q80_80_33",
490 .cfg = &flashcfg_fm_q80,
491 },
492 {
493 .jedec_id = 0x1570EF,
494 .name = "Winb_16JV_16_33",
495 .cfg = &flashcfg_winb_16jv,
496 },
497 {
498 .jedec_id = 0x1870EF,
499 .name = "Winb_128JV_128_33",
500 .cfg = &flashcfg_winb_16jv,
501 },
502 {
503 .jedec_id = 0x15605E,
504 .name = "ZB_VQ16_16_33",
505 .cfg = &flashcfg_winb_16jv,
506 },
507 {
508 .jedec_id = 0x144020,
509 .name = "XM_25QH80_80_33",
510 .cfg = &flashcfg_winb_16jv,
511 },
512 {
513 .jedec_id = 0x154020,
514 .name = "XM_25QH16_16_33",
515 .cfg = &flashcfg_winb_16jv,
516 },
517 {
518 .jedec_id = 0x164020,
519 .name = "XM_25QH32_32_33",
520 .cfg = &flashcfg_winb_16jv,
521 },
522 {
523 .jedec_id = 0x174020,
524 .name = "XM_25QH64_64_33",
525 .cfg = &flashcfg_winb_16jv,
526 },
527 {
528 .jedec_id = 0x13325E,
529 .name = "ZB_D40B_80_33",
530 .cfg = &flashcfg_mx_kh25,
531 },
532 {
533 .jedec_id = 0x14325E,
534 .name = "ZB_D80B_80_33",
535 .cfg = &flashcfg_mx_kh25,
536 },
537 {
538 .jedec_id = 0x15405E,
539 .name = "ZB_25Q16B_15_33",
540 .cfg = &flashcfg_winb_16jv,
541 },
542 {
543 .jedec_id = 0x16405E,
544 .name = "ZB_25Q32B_16_33",
545 .cfg = &flashcfg_winb_16jv,
546 },
547 {
548 .jedec_id = 0x1560EB,
549 .name = "TH_25Q16HB_16_33",
550 .cfg = &flashcfg_fm_q80,
551 },
552 {
553 .jedec_id = 0x15345E,
554 .name = "ZB_25Q16A_15_33",
555 .cfg = &flashcfg_winb_16jv,
556 },
557 };
558
559 /*@} end of group SF_CFG_EXT_Private_Variables */
560
561 /** @defgroup SF_CFG_EXT_Global_Variables
562 * @{
563 */
564
565 /*@} end of group SF_CFG_EXT_Global_Variables */
566
567 /** @defgroup SF_CFG_EXT_Private_Fun_Declaration
568 * @{
569 */
570
571 /*@} end of group SF_CFG_EXT_Private_Fun_Declaration */
572
573 /** @defgroup SF_CFG_EXT_Public_Functions
574 * @{
575 */
576
577 /****************************************************************************/ /**
578 * @brief Init internal flash GPIO
579 *
580 * @param None
581 *
582 * @return None
583 *
584 *******************************************************************************/
bflb_sf_cfg_Init_Internal_Flash_Gpio(void)585 void ATTR_TCM_SECTION bflb_sf_cfg_Init_Internal_Flash_Gpio(void)
586 {
587 GLB_GPIO_Cfg_Type gpioCfg = {
588 .gpioPin = GLB_GPIO_PIN_0,
589 .gpioFun = GPIO_FUN_GPIO,
590 .gpioMode = GPIO_MODE_INPUT,
591 .pullType = GPIO_PULL_NONE,
592 .drive = 0,
593 .smtCtrl = 1,
594 };
595
596 /* Turn on Flash pad, GPIO23 - GPIO28 */
597 for (uint32_t pin = 23; pin < 29; pin++) {
598 gpioCfg.gpioPin = pin;
599
600 if (pin == 25) {
601 gpioCfg.pullType = GPIO_PULL_DOWN;
602 } else {
603 gpioCfg.pullType = GPIO_PULL_NONE;
604 }
605
606 GLB_GPIO_Init(&gpioCfg);
607 }
608 }
609
610 /****************************************************************************/ /**
611 * @brief Get flash config according to flash ID
612 *
613 * @param flash_id: Flash ID
614 * @param p_flash_cfg: Flash config pointer
615 * @param group: CPU group id 0 or 1
616 * @param bank: Flash bank select
617 *
618 * @return BFLB_RET:0 means success and other value means error
619 *
620 *******************************************************************************/
bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id,spi_flash_cfg_type * p_flash_cfg,uint8_t group,uint8_t bank)621 int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
622 uint8_t group, uint8_t bank)
623 {
624 uint32_t i;
625 uint8_t buf[sizeof(spi_flash_cfg_type) + 8];
626 uint32_t crc, *pCrc;
627 char flash_cfg_magic[] = "FCFG";
628
629 if (flash_id == 0) {
630 bflb_xip_sflash_read_via_cache_need_lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(spi_flash_cfg_type) + 8, group, bank);
631
632 if (BL702_MemCmp(buf, flash_cfg_magic, 4) == 0) {
633 crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(spi_flash_cfg_type));
634 pCrc = (uint32_t *)(buf + 4 + sizeof(spi_flash_cfg_type));
635
636 if (*pCrc == crc) {
637 BL702_MemCpy_Fast(p_flash_cfg, (uint8_t *)buf + 4, sizeof(spi_flash_cfg_type));
638 return SUCCESS;
639 }
640 }
641 } else {
642 if (bflb_sf_cfg_get_flash_cfg_need_lock(flash_id, p_flash_cfg, group, bank) == SUCCESS) {
643 /* 0x134051 flash cfg is wrong in rom, find again */
644 if ((flash_id&0xFFFFFF) != 0x134051) {
645 return SUCCESS;
646 }
647 }
648
649 for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) {
650 if (flash_infos[i].jedec_id == flash_id) {
651 BL702_MemCpy_Fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type));
652 return SUCCESS;
653 }
654 }
655 }
656
657 return ERROR;
658 }
659
660 /****************************************************************************/ /**
661 * @brief Identify one flash
662 *
663 * @param call_from_flash: code run at flash or ram
664 * @param auto_scan: Auto scan all GPIO pin
665 * @param flash_pin_cfg: Specify flash GPIO config, not auto scan
666 * @param restore_default: Wether restore default flash GPIO config
667 * @param p_flash_cfg: Flash config pointer
668 * @param group: CPU group id 0 or 1
669 * @param bank: Flash bank select
670 *
671 * @return Flash ID
672 *
673 *******************************************************************************/
bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash,uint8_t flash_pin_cfg,uint8_t restore_default,spi_flash_cfg_type * p_flash_cfg,uint8_t group,uint8_t bank)674 uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg,
675 uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
676 {
677 uint32_t jedec_id = 0;
678 uint32_t i = 0;
679 uint32_t ret = 0;
680
681 ret = bflb_sf_cfg_flash_identify(call_from_flash, flash_pin_cfg, restore_default, p_flash_cfg, group, bank);
682
683 if ((ret & BFLB_FLASH_ID_VALID_FLAG) != 0) {
684 /* 0x134051 flash cfg is wrong in rom, find again */
685 if ((ret&0xFFFFFF) != 0x134051) {
686 return ret;
687 }
688 }
689
690 jedec_id = (ret & 0xffffff);
691
692 for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) {
693 if (flash_infos[i].jedec_id == jedec_id) {
694 BL702_MemCpy_Fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type));
695 break;
696 }
697 }
698
699 if (i == sizeof(flash_infos) / sizeof(flash_infos[0])) {
700 return jedec_id;
701 } else {
702 return (jedec_id | BFLB_FLASH_ID_VALID_FLAG);
703 }
704 }
705
706 /*@} end of group SF_CFG_EXT_Public_Functions */
707
708 /*@} end of group SF_CFG_EXT */
709
710 /*@} end of group BL702_Peripheral_Driver */
711