1 /** 2 ****************************************************************************** 3 * @file bl808_glb_gpio.h 4 * @version V1.0 5 * @date 6 * @brief This file is the standard driver header file 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __BL808_GLB_GPIO_H__ 37 #define __BL808_GLB_GPIO_H__ 38 39 #include "glb_reg.h" 40 #include "mm_glb_reg.h" 41 #include "pds_reg.h" 42 #include "bl808_gpio.h" 43 #include "bl808_hbn.h" 44 #include "bl808_aon.h" 45 #include "bl808_pds.h" 46 #include "bl808_common.h" 47 #include "bflb_sf_ctrl.h" 48 #include "bflb_sf_cfg.h" 49 50 /** @addtogroup BL808_Peripheral_Driver 51 * @{ 52 */ 53 54 /** @addtogroup GLB_GPIO 55 * @{ 56 */ 57 58 /** @defgroup GLB_GPIO_Public_Types 59 * @{ 60 */ 61 62 /** 63 * @brief GLB GPIO interrupt control mode type definition 64 */ 65 typedef enum { 66 GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE = 0, /*!< GPIO interrupt sync mode, GPIO falling edge trigger interrupt */ 67 GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE = 1, /*!< GPIO interrupt sync mode, GPIO rising edge trigger interrupt */ 68 GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL = 2, /*!< GPIO interrupt sync mode, GPIO low level trigger interrupt (32k 3T) */ 69 GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL = 3, /*!< GPIO interrupt sync mode, GPIO high level trigger interrupt (32k 3T) */ 70 GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE = 4, /*!< GPIO interrupt sync mode, GPIO falling and rising edge trigger interrupt */ 71 GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE = 8, /*!< GPIO interrupt async mode, GPIO falling edge trigger interrupt */ 72 GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE = 9, /*!< GPIO interrupt async mode, GPIO rising edge trigger interrupt */ 73 GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL = 10, /*!< GPIO interrupt async mode, GPIO low level trigger interrupt (32k 3T) */ 74 GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL = 11, /*!< GPIO interrupt async mode, GPIO high level trigger interrupt (32k 3T) */ 75 } GLB_GPIO_INT_TRIG_Type; 76 77 /** 78 * @brief GLB GPIO FIFO interrupt type definition 79 */ 80 typedef enum { 81 GLB_GPIO_FIFO_INT_FER, /*!< GLB GPIO FIFO Underflow or Overflow interrupt */ 82 GLB_GPIO_FIFO_INT_FIFO, /*!< GLB GPIO FIFO ready (tx_fifo_cnt > tx_fifo_th) interrupt */ 83 GLB_GPIO_FIFO_INT_END, /*!< GLB GPIO FIFO Empty interrupt */ 84 GLB_GPIO_FIFO_INT_ALL, /*!< All the interrupt */ 85 } GLB_GPIO_FIFO_INT_Type; 86 87 /** 88 * @brief GLB GPIO FIFO Timing Phase type definition 89 */ 90 typedef enum { 91 GPIO_FIFO_PHASE_FIRST_HIGH, /*!< GPIO first send high level */ 92 GPIO_FIFO_PHASE_FIRST_LOW, /*!< GPIO first send low level */ 93 } GLB_GPIO_FIFO_PHASE_Type; 94 95 /** 96 * @brief GLB GPIO FIFO Idle State type definition 97 */ 98 typedef enum { 99 GPIO_FIFO_IDLE_LOW, 100 GPIO_FIFO_IDLE_HIGH, 101 } GLB_GPIO_FIFO_IDLE_Type; 102 103 /** 104 * @brief GLB GPIO FIFO Latch Mode type definition 105 */ 106 typedef enum { 107 GPIO_FIFO_LATCH_WRITE, /*!< GPIO FIFO direct write I/O */ 108 GPIO_FIFO_LATCH_SETCLEAR, /*!< GPIO FIFO set/clr I/O */ 109 } GLB_GPIO_FIFO_LATCH_Type; 110 111 /** 112 * @brief GPIO interrupt configuration structure type definition 113 */ 114 typedef struct 115 { 116 GLB_GPIO_Type gpioPin; /*!< GPIO pin num */ 117 GLB_GPIO_INT_TRIG_Type trig; /*!< GPIO interrupt trig mode */ 118 BL_Mask_Type intMask; /*!< GPIO interrupt mask config */ 119 } GLB_GPIO_INT_Cfg_Type; 120 121 /** 122 * @brief UART configuration structure type definition 123 */ 124 typedef struct 125 { 126 uint8_t code0FirstTime; /*!< The clock num of code0 first send */ 127 uint8_t code1FirstTime; /*!< The clock num of code1 first send */ 128 uint16_t codeTotalTime; /*!< The total clock num of code0/1(high + low */ 129 GLB_GPIO_FIFO_PHASE_Type code0Phase; /*!< low or high level of code0 first send */ 130 GLB_GPIO_FIFO_PHASE_Type code1Phase; /*!< low or high level of code1 first send */ 131 GLB_GPIO_FIFO_IDLE_Type idle; /*!< the I/O idle level */ 132 uint8_t fifoDmaThreshold; /*!< FIFO threshold */ 133 BL_Fun_Type fifoDmaEnable; /*!< Enable or disable DMA of GPIO */ 134 GLB_GPIO_FIFO_LATCH_Type latch; /*!< Write or set/clr GPIO level */ 135 } GLB_GPIO_FIFO_CFG_Type; 136 137 /*@} end of group GLB_GPIO_Public_Types */ 138 139 /** @defgroup GLB_GPIO_Public_Constants 140 * @{ 141 */ 142 143 /** @defgroup GLB_GPIO_INT_TRIG_TYPE 144 * @{ 145 */ 146 #define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE) || \ 147 ((type) == GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE) || \ 148 ((type) == GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL) || \ 149 ((type) == GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL) || \ 150 ((type) == GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE) || \ 151 ((type) == GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE) || \ 152 ((type) == GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE) || \ 153 ((type) == GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL) || \ 154 ((type) == GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL)) 155 156 /** @defgroup GLB_GPIO_INT_TRIG_TYPE 157 * @{ 158 */ 159 #define IS_GLB_GPIO_FIFO_INT_TYPE(type) (((type) == GLB_GPIO_INT_FER) || \ 160 ((type) == GLB_GPIO_INT_FIFO) || \ 161 ((type) == GLB_GPIO_INT_END) || \ 162 ((type) == GLB_GPIO_FIFO_INT_ALL)) 163 164 /** @defgroup GLB_GPIO_FIFO_PHASE_TYPE 165 * @{ 166 */ 167 #define IS_GLB_GPIO_FIFO_PHASE_TYPE(type) (((type) == GPIO_FIFO_HIGH_FIRST_LOW_FOLLOWED) || \ 168 ((type) == GPIO_FIFO_LOW_FIRST_HIGH_FOLLOWED)) 169 170 /** @defgroup GLB_GPIO_FIFO_PHASE_TYPE 171 * @{ 172 */ 173 #define IS_GLB_GPIO_FIFO_LATCH_TYPE(type) (((type) == GPIO_FIFO_LATCH_WRITE) || \ 174 ((type) == GPIO_FIFO_LATCH_SETCLEAR)) 175 176 /*@} end of group GLB_GPIO_Public_Constants */ 177 178 /** @defgroup GLB_GPIO_Public_Macros 179 * @{ 180 */ 181 182 /*@} end of group GLB_GPIO_Public_Macros */ 183 184 /** @defgroup GLB_GPIO_Public_Functions 185 * @{ 186 */ 187 /*----------*/ 188 #ifndef BFLB_USE_HAL_DRIVER 189 void GPIO_INT0_IRQHandler(void); 190 #endif 191 /*----------*/ 192 BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg); 193 BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt); 194 BL_Err_Type GLB_GPIO_Input_Enable(GLB_GPIO_Type gpioPin); 195 BL_Err_Type GLB_Embedded_Flash_Pad_Enable(void); 196 BL_Err_Type GLB_GPIO_Input_Disable(GLB_GPIO_Type gpioPin); 197 BL_Err_Type GLB_GPIO_Output_Enable(GLB_GPIO_Type gpioPin); 198 BL_Err_Type GLB_GPIO_Output_Disable(GLB_GPIO_Type gpioPin); 199 BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin); 200 uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin); 201 uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin); 202 BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val); 203 BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin); 204 BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin); 205 BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg); 206 BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask); 207 BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin); 208 BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin); 209 BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void); 210 BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun); 211 212 #ifndef BFLB_USE_HAL_DRIVER 213 void GPIO_FIFO_IRQHandler(void); 214 #endif 215 BL_Err_Type GLB_GPIO_Fifo_Callback_Install(GLB_GPIO_FIFO_INT_Type intType, intCallback_Type *cbFun); 216 BL_Err_Type GLB_GPIO_Fifo_IRQHandler_Install(void); 217 BL_Err_Type GLB_GPIO_Fifo_Init(GLB_GPIO_FIFO_CFG_Type *cfg); 218 BL_Err_Type GLB_GPIO_Fifo_Push(uint16_t *data, uint16_t len); 219 uint32_t GLB_GPIO_Fifo_GetCount(void); 220 BL_Err_Type GLB_GPIO_Fifo_Clear(void); 221 BL_Err_Type GLB_GPIO_Fifo_IntMask(GLB_GPIO_FIFO_INT_Type intType, BL_Mask_Type intMask); 222 BL_Err_Type GLB_GPIO_Fifo_IntClear(GLB_GPIO_FIFO_INT_Type intType); 223 BL_Sts_Type GLB_GPIO_Fifo_GetIntStatus(GLB_GPIO_FIFO_INT_Type intType); 224 BL_Sts_Type GLB_GPIO_Fifo_Enable(void); 225 BL_Sts_Type GLB_GPIO_Fifo_Disable(void); 226 227 /*@} end of group GLB_GPIO_Public_Functions */ 228 229 /*@} end of group GLB_GPIO */ 230 231 /*@} end of group BL808_Peripheral_Driver */ 232 233 #endif /* __BL808_GLB_GPIO_H__ */ 234