1 #ifndef __BL808_MEMORYMAP_H
2 #define __BL808_MEMORYMAP_H
3 
4 /****************************************************************************
5  * Included Files
6  ****************************************************************************/
7 
8 /****************************************************************************
9  * Pre-processor Definitions
10  ****************************************************************************/
11 #define BL808_OCRAM_BASE           (0x22020000)
12 #define BL808_OCRAM_END            (0x22020000 + 64 * 1024)
13 #define BL808_OCRAM_CACHEABLE_BASE (0x62020000)
14 #define BL808_OCRAM_CACHEABLE_END  (0x62020000 + 64 * 1024)
15 
16 #define BL808_WRAM_BASE           (0x22030000)
17 #define BL808_WRAM_END            (0x22030000 + 160 * 1024)
18 #define BL808_WRAM_CACHEABLE_BASE (0x62030000)
19 #define BL808_WRAM_CACHEABLE_END  (0x62030000 + 160 * 1024)
20 
21 #define BL808_MCU_ALLRAM_BASE           (0x22020000)
22 #define BL808_MCU_ALLRAM_END            (0x22020000 + 64 * 1024 + 160 * 1024)
23 #define BL808_MCU_ALLRAM_CACHEABLE_BASE (0x62020000)
24 #define BL808_MCU_ALLRAM_CACHEABLE_END  (0x62020000 + 64 * 1024 + 160 * 1024)
25 
26 #define BL808_DRAM_BASE           (0x3EF80000)
27 #define BL808_DRAM_END            (0x3EF80000 + 512 * 1024)
28 #define BL808_DRAM_CACHEABLE_BASE (0x7EF80000)
29 #define BL808_DRAM_CACHEABLE_END  (0x7EF80000 + 512 * 1024)
30 
31 #define BL808_VRAM_BASE           (0x3F000000)
32 #define BL808_VRAM_END            (0x3F000000 + 32 * 1024)
33 #define BL808_VRAM_CACHEABLE_BASE (0x7F000000)
34 #define BL808_VRAM_CACHEABLE_END  (0x7F000000 + 32 * 1024)
35 
36 #define BL808_MM_ALLRAM_BASE           (0x3EF80000)
37 #define BL808_MM_ALLRAM_END            (0x3EF80000 + 512 * 1024 + 32 * 1024)
38 #define BL808_MM_ALLRAM_CACHEABLE_BASE (0x7EF80000)
39 #define BL808_MM_ALLRAM_CACHEABLE_END  (0x7EF80000 + 512 * 1024 + 32 * 1024)
40 
41 #define BL808_FLASH_XIP_BASE         (0x58000000)
42 #define BL808_FLASH_XIP_END          (0x58000000 + 64 * 1024 * 1024)
43 #define BL808_FLASH2_XIP_BASE        (0x5C000000)
44 #define BL808_FLASH2_XIP_END         (0x5C000000 + 64 * 1024 * 1024)
45 #define BL808_FLASH_XIP_REMAP0_BASE  (0xD8000000)
46 #define BL808_FLASH_XIP_REMAP0_END   (0xD8000000 + 64 * 1024 * 1024)
47 #define BL808_FLASH2_XIP_REMAP0_BASE (0xDC000000)
48 #define BL808_FLASH2_XIP_REMAP0_END  (0xDC000000 + 64 * 1024 * 1024)
49 
50 #define BL808_MM_WHOLERAM_BASE           (0x3EF80000)
51 #define BL808_MM_WHOLERAM_END            (0x3EF80000 + 512 * 1024 + 96 * 1024)
52 #define BL808_MM_WHOLERAM_CACHEABLE_BASE (0x7EF80000)
53 #define BL808_MM_WHOLERAM_CACHEABLE_END  (0x7EF80000 + 512 * 1024 + 96 * 1024)
54 
55 /*@} end of group Memory_Map_Section */
56 
57 /* BL808 peripherals base address */
58 /* WLSYS */
59 #define GLB_BASE         ((uint32_t)0x20000000)
60 #define MIX_BASE         ((uint32_t)0x20001000)
61 #define GPIP_BASE        ((uint32_t)0x20002000)
62 #define PHY_BASE         ((uint32_t)0x20002800)
63 #define AGC_BASE         ((uint32_t)0x20002c00)
64 #define SEC_DBG_BASE     ((uint32_t)0x20003000)
65 #define SEC_ENG_BASE     ((uint32_t)0x20004000)
66 #define TZ1_BASE         ((uint32_t)0x20005000)
67 #define TZC_SEC_BASE     ((uint32_t)0x20005000)
68 #define TZ2_BASE         ((uint32_t)0x20006000)
69 #define TZC_NSEC_BASE    ((uint32_t)0x20006000)
70 #define EFUSE_BASE       ((uint32_t)0x20056000)
71 #define EF_DATA_BASE     ((uint32_t)0x20056000)
72 #define EF_CTRL_BASE     ((uint32_t)0x20056000)
73 #define CCI_BASE         ((uint32_t)0x20008000)
74 #define MCU_MISC_BASE    ((uint32_t)0x20009000)
75 #define L1C_BASE         ((uint32_t)0x20009000)
76 #define UART0_BASE       ((uint32_t)0x2000a000)
77 #define UART1_BASE       ((uint32_t)0x2000a100)
78 #define SPI0_BASE        ((uint32_t)0x2000a200)
79 #define I2C0_BASE        ((uint32_t)0x2000a300)
80 #define PWM_BASE         ((uint32_t)0x2000a400)
81 #define TIMER0_BASE      ((uint32_t)0x2000a500)
82 #define IR_BASE          ((uint32_t)0x2000a600)
83 #define CKS_BASE         ((uint32_t)0x2000a700)
84 #define IPC0_BASE        ((uint32_t)0x2000a800)
85 #define IPC1_BASE        ((uint32_t)0x2000a840)
86 #define I2C1_BASE        ((uint32_t)0x2000a900)
87 #define UART2_BASE       ((uint32_t)0x2000aa00)
88 #define I2S_BASE         ((uint32_t)0x2000ab00)
89 #define PDM0_BASE        ((uint32_t)0x2000a000)
90 #define LZ4D_BASE        ((uint32_t)0x2000ad00)
91 #define QSPI_BASE        ((uint32_t)0x2000b000)
92 #define SF_CTRL_BASE     ((uint32_t)0x2000b000)
93 #define SF_CTRL_BUF_BASE ((uint32_t)0x2000b600)
94 #define DMA0_BASE        ((uint32_t)0x2000c000)
95 #define PDS_BASE         ((uint32_t)0x2000e000)
96 #define HBN_BASE         ((uint32_t)0x2000f000)
97 #define AON_BASE         ((uint32_t)0x2000f000)
98 #define EMI_MISC_BASE    ((uint32_t)0x20050000)
99 #define PSRAM_CTRL_BASE  ((uint32_t)0x20052000)
100 #define USB_BASE         ((uint32_t)0x20072000)
101 #define AUDIO_BASE       ((uint32_t)0x20055000)
102 #define SDH_BASE         ((uint32_t)0x20060000)
103 #define EMAC_BASE        ((uint32_t)0x20070000)
104 #define DMA1_BASE        ((uint32_t)0x20071000)
105 
106 /* MMSYS */
107 #define MM_MISC_BASE     ((uint32_t)0x30000000)
108 #define DMA2_BASE        ((uint32_t)0x30001000)
109 #define UART3_BASE       ((uint32_t)0x30002000)
110 #define I2C2_BASE        ((uint32_t)0x30003000)
111 #define I2C3_BASE        ((uint32_t)0x30004000)
112 #define IPC2_BASE        ((uint32_t)0x30005000)
113 #define DMA2D_BASE       ((uint32_t)0x30006000)
114 #define CLKRST_CTRL_BASE ((uint32_t)0x30007000)
115 #define MM_GLB_BASE      ((uint32_t)0x30007000)
116 #define SPI1_BASE        ((uint32_t)0x30008000)
117 #define TIMER1_BASE      ((uint32_t)0x30009000)
118 #define PSRAM_UHS_BASE   ((uint32_t)0x3000f000)
119 
120 /* MM_SUBSYS */
121 #define CAM_FRONT_BASE       ((uint32_t)0x30010000)
122 #define MM_SUBSYS_BASE       ((uint32_t)0x30011000)
123 #define DVP0_BASE            ((uint32_t)0x30012000)
124 #define DVP1_BASE            ((uint32_t)0x30012100)
125 #define DVP2_BASE            ((uint32_t)0x30012200)
126 #define DVP3_BASE            ((uint32_t)0x30012300)
127 #define DVP4_BASE            ((uint32_t)0x30012400)
128 #define DVP5_BASE            ((uint32_t)0x30012500)
129 #define DVP6_BASE            ((uint32_t)0x30012600)
130 #define DVP7_BASE            ((uint32_t)0x30012700)
131 #define DVP_TSRC0_BASE       ((uint32_t)0x30012800)
132 #define DVP_TSRC1_BASE       ((uint32_t)0x30012900)
133 #define AXI_CTRL_NR3D_BASE   ((uint32_t)0x30012a00)
134 #define OSD_PROBE_BASE       ((uint32_t)0x30012b00)
135 #define OSD_A_BASE           ((uint32_t)0x30013000)
136 #define OSD_B_BASE           ((uint32_t)0x30014000)
137 #define OSD_DP_BASE          ((uint32_t)0x30015000)
138 #define OSD_BLEND0_OFFSET    (0x000)
139 #define OSD_BLEND1_OFFSET    (0x100)
140 #define OSD_BLEND2_OFFSET    (0x200)
141 #define OSD_BLEND3_OFFSET    (0x300)
142 #define OSD_DRAW_LOW_OFFSET  (0x400)
143 #define OSD_DRAW_HIGH_OFFSET (0x504)
144 #define MIPI_BASE            ((uint32_t)0x3001a000)
145 #define DBI_BASE             ((uint32_t)0x3001b000)
146 #define DSI_BASE             ((uint32_t)0x3001a100)
147 #define CSI_BASE             ((uint32_t)0x3001a000)
148 
149 /* CODEC_SUBSYS */
150 #define CODEC_MISC_BASE ((uint32_t)0x30020000)
151 #define MJPEG_BASE      ((uint32_t)0x30021000)
152 #define VIDEO_BASE      ((uint32_t)0x30022000)
153 #define MJPEG_DEC_BASE  ((uint32_t)0x30023000)
154 #define BL_CNN_BASE     ((uint32_t)0x30024000)
155 
156 #define HBN_RAM_BASE ((uint32_t)0x20010000)
157 
158 #define RF_BASE ((uint32_t)0x20001000)
159 
160 #endif