1/*
2* Copyright 2019 ETH Zürich and University of Bologna
3*
4* Licensed under the Apache License, Version 2.0 (the "License");
5* you may not use this file except in compliance with the License.
6* You may obtain a copy of the License at
7*
8*     http://www.apache.org/licenses/LICENSE-2.0
9*
10* Unless required by applicable law or agreed to in writing, software
11* distributed under the License is distributed on an "AS IS" BASIS,
12* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13* See the License for the specific language governing permissions and
14* limitations under the License.
15*
16* SPDX-License-Identifier: Apache-2.0
17* Author: Robert Balas (balasr@iis.ee.ethz.ch)
18* Change Logs:
19* Date           Author       Notes
20* 2022-12-08     WangShun     Remove FreeRTOS related code and add RT-Thread code
21*/
22.extern SW_handler
23#ifdef PULP_FREERTOS_VECTORED_CONTEXT_SWITCH
24.extern	freertos_risc_v_ctxt_handler
25#endif
26#ifdef __HACK_FIRMWARE_OPT1 /* TODO: properly do this with weak symbols */
27.extern TIMER1_IRQ_handler
28#endif
29.extern fc_soc_event_handler
30.section .vectors, "ax"
31.option norvc
32vector_table:
33	j SW_handler  // irq0
34	j SW_handler
35	j SW_handler
36	j SW_handler  // irq3
37	j SW_handler
38	j SW_handler
39	j SW_handler
40	j SW_handler //ctxt_handler  // irq 7 mtime or timer
41	j SW_handler
42	j SW_handler
43	j SW_handler // SW_handler
44	j SW_handler // irq 11 Machine (event Fifo)
45	j SW_handler
46	j SW_handler
47	j SW_handler
48	j SW_handler
49	j SW_handler // IRQ16
50	j SW_handler // IRQ17
51	j SW_handler // IRQ18
52	j SW_handler // IRQ19
53	j SW_handler // IRQ20
54	j SW_handler // IRQ21
55	j SW_handler // IRQ22
56	j SW_handler // IRQ23
57	j SW_handler // IRQ24
58	j SW_handler // IRQ25
59	j SW_handler // IRQ26
60	j SW_handler // IRQ27
61	j SW_handler // IRQ28
62	j SW_handler // IRQ29
63	j SW_handler // IRQ30
64    j SW_handler // IRQ30
65
66/* this is fixed to 0x8000, used for PULP_SECURE=0. We redirect this entry to the
67new vector table (which is at mtvec) */
68/* .section .legacy_irq, "ax" */
69/*	j vector_table */
70/*	j __no_irq_handler */
71/*	j __no_irq_handler */
72/*	j __no_irq_handler */
73
74.section .text.vecs
75/* exception handling */
76__no_irq_handler:
77	la a0, no_exception_handler_msg
78	jal ra, puts
79	j __no_irq_handler
80
81sw_irq_handler:
82	csrr t0, mcause
83	slli t0, t0, 1  /* shift off the high bit */
84	srli t0, t0, 1
85	li t1, 2
86	beq t0, t1, handle_illegal_insn
87	li t1, 11
88	beq t0, t1, handle_ecall
89	li t1, 3
90	beq t0, t1, handle_ebreak
91	j handle_unknown
92
93handle_ecall:
94	la a0, ecall_msg
95	jal ra, puts
96	j end_handler
97
98handle_ebreak:
99	la a0, ebreak_msg
100	jal ra, puts
101	j end_handler
102
103handle_illegal_insn:
104	la a0, illegal_insn_msg
105	jal ra, puts
106	j end_handler
107
108handle_unknown:
109	la a0, unknown_msg
110	jal ra, puts
111	j end_handler
112
113end_handler:
114	csrr a0, mepc
115	addi a0, a0, 4
116	csrw mepc, a0
117	mret
118
119.section .rodata
120illegal_insn_msg:
121	.string "illegal instruction exception handler entered\n"
122ecall_msg:
123	.string "ecall exception handler entered\n"
124ebreak_msg:
125	.string "ebreak exception handler entered\n"
126unknown_msg:
127	.string "unknown exception handler entered\n"
128no_exception_handler_msg:
129	.string "no exception handler installed\n"
130