1 /*
2  * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2021-11-16     Dystopia     the first version
9  */
10 
11 #ifndef __C66XX_H__
12 #define __C66XX_H__
13 
14 extern __cregister volatile unsigned int IERR;    /* Internal Exception Report Register */
15 extern __cregister volatile unsigned int ECR;     /* Exception Clear Register */
16 extern __cregister volatile unsigned int EFR;     /* Exception Flag Register */
17 extern __cregister volatile unsigned int TSR;     /* Task State Register */
18 extern __cregister volatile unsigned int ITSR;    /* Interrupt Task State Register */
19 extern __cregister volatile unsigned int NTSR;    /* NMI/exception Task State Register */
20 extern __cregister volatile unsigned int TSCL;    /* Time Stamp Counter Register - Low Half  */
21 extern __cregister volatile unsigned int TSCH;    /* Time Stamp Counter Register - High Half */
22 extern __cregister volatile unsigned int DNUM;    /* Core number */
23 
24 extern __cregister volatile unsigned int AMR;
25 extern __cregister volatile unsigned int CSR;
26 extern __cregister volatile unsigned int IFR;
27 extern __cregister volatile unsigned int ISR;
28 extern __cregister volatile unsigned int ICR;
29 extern __cregister volatile unsigned int IER;
30 extern __cregister volatile unsigned int ISTP;
31 extern __cregister volatile unsigned int IRP;
32 extern __cregister volatile unsigned int NRP;
33 
34 #ifdef _BIG_ENDIAN
35 #define RT_REG_PAIR(odd, even) unsigned long odd; unsigned long even
36 #else
37 #define RT_REG_PAIR(odd, even) unsigned long even; unsigned long odd
38 #endif
39 
40 struct rt_hw_register
41 {
42     RT_REG_PAIR(b17, b16);
43     RT_REG_PAIR(b19, b18);
44     RT_REG_PAIR(b21, b20);
45     RT_REG_PAIR(b23, b22);
46     RT_REG_PAIR(b25, b24);
47     RT_REG_PAIR(b27, b26);
48     RT_REG_PAIR(b29, b28);
49     RT_REG_PAIR(b31, b30);
50 
51     RT_REG_PAIR(b1, b0);
52     RT_REG_PAIR(b3, b2);
53     RT_REG_PAIR(b5, b4);
54     RT_REG_PAIR(b7, b6);
55     RT_REG_PAIR(b9, b8);
56     RT_REG_PAIR(b11, b10);
57     RT_REG_PAIR(b13, b12);
58 
59     RT_REG_PAIR(a17, a16);
60     RT_REG_PAIR(a19, a18);
61     RT_REG_PAIR(a21, a20);
62     RT_REG_PAIR(a23, a22);
63     RT_REG_PAIR(a25, a24);
64     RT_REG_PAIR(a27, a26);
65     RT_REG_PAIR(a29, a28);
66     RT_REG_PAIR(a31, a30);
67 
68     RT_REG_PAIR(a1, a0);
69     RT_REG_PAIR(a3, a2);
70     RT_REG_PAIR(a5, a4);
71     RT_REG_PAIR(a7, a6);
72     RT_REG_PAIR(a9, a8);
73     RT_REG_PAIR(a11, a10);
74     RT_REG_PAIR(a13, a12);
75 
76     RT_REG_PAIR(a15, a14);
77     RT_REG_PAIR(sp, dp);
78 };
79 
80 typedef struct rt_hw_exp_stack_register
81 {
82     RT_REG_PAIR(tsr, orig_a4);
83     RT_REG_PAIR(rilc, ilc);
84     RT_REG_PAIR(pc, csr);
85     struct rt_hw_register hw_register;
86 } rt_hw_thread_stack_register;
87 
88 #define __dint()                asm(" DINT")
89 #define __rint()                asm(" RINT")
90 #define __system_call()         asm(" SWE")
91 #define __enter_idle()          asm(" IDLE")
92 #define __nop()                 asm(" NOP")
93 #define __mfence()              asm(" MFENCE")
94 
95 #define __SYSREG(ADDR, TYPE)    (*(volatile TYPE*)(ADDR))
96 #define __SYSREGA(ADDR, TYPE)   ((volatile TYPE*)(ADDR))
97 
98 #endif /* __C66XX_H__ */
99