1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: ccm_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for ccm module.
ccm_iomux_config(void)34 void ccm_iomux_config(void)
35 {
36 // Config ccm.CCM_CLKO1 to pad GPIO00(T5)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(0x00000000);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(0x0001B0B0);
39 // Mux Register:
40 // IOMUXC_SW_MUX_CTL_PAD_GPIO00(0x020E020C)
41 // SION [4] - Software Input On Field Reset: DISABLED
42 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
43 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
44 // ENABLED (1) - Force input path of pad.
45 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
46 // Select iomux modes to be used for pad.
47 // ALT0 (0) - Select instance: ccm signal: CCM_CLKO1
48 // ALT2 (2) - Select instance: kpp signal: KEY_COL5
49 // ALT3 (3) - Select instance: asrc signal: ASRC_EXT_CLK
50 // ALT4 (4) - Select instance: epit1 signal: EPIT1_OUT
51 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO00
52 // ALT6 (6) - Select instance: usb signal: USB_H1_PWR
53 // ALT7 (7) - Select instance: snvs signal: SNVS_VIO_5
54 HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(
55 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION_V(DISABLED) |
56 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE_V(ALT0));
57 // Pad Control Register:
58 // IOMUXC_SW_PAD_CTL_PAD_GPIO00(0x020E05DC)
59 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
60 // DISABLED (0) - CMOS input
61 // ENABLED (1) - Schmitt trigger input
62 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
63 // 100K_OHM_PD (0) - 100K Ohm Pull Down
64 // 47K_OHM_PU (1) - 47K Ohm Pull Up
65 // 100K_OHM_PU (2) - 100K Ohm Pull Up
66 // 22K_OHM_PU (3) - 22K Ohm Pull Up
67 // PUE [13] - Pull / Keep Select Field Reset: PULL
68 // KEEP (0) - Keeper Enabled
69 // PULL (1) - Pull Enabled
70 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
71 // DISABLED (0) - Pull/Keeper Disabled
72 // ENABLED (1) - Pull/Keeper Enabled
73 // ODE [11] - Open Drain Enable Field Reset: DISABLED
74 // Enables open drain of the pin.
75 // DISABLED (0) - Output is CMOS.
76 // ENABLED (1) - Output is Open Drain.
77 // SPEED [7:6] - Speed Field Reset: 100MHZ
78 // NOTE: Read Only Field
79 // The value of this field is fixed and cannot be changed.
80 // RESERVED0 (0) - Reserved
81 // 50MHZ (1) - Low (50 MHz)
82 // 100MHZ (2) - Medium (100 MHz)
83 // 200MHZ (3) - Maximum (200 MHz)
84 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
85 // HIZ (0) - HI-Z
86 // 240_OHM (1) - 240 Ohm
87 // 120_OHM (2) - 120 Ohm
88 // 80_OHM (3) - 80 Ohm
89 // 60_OHM (4) - 60 Ohm
90 // 48_OHM (5) - 48 Ohm
91 // 40_OHM (6) - 40 Ohm
92 // 34_OHM (7) - 34 Ohm
93 // SRE [0] - Slew Rate Field Reset: SLOW
94 // Slew rate control.
95 // SLOW (0) - Slow Slew Rate
96 // FAST (1) - Fast Slew Rate
97 HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(
98 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS_V(ENABLED) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS_V(100K_OHM_PU) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE_V(PULL) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE_V(ENABLED) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE_V(DISABLED) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE_V(40_OHM) |
104 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE_V(SLOW));
105 }
106