1 /*
2 *********************************************************************************************************
3 *                                                AR100 SYSTEM
4 *                                     AR100 Software System Develop Kits
5 *                                         clock control unit module
6 *
7 *                                    (c) Copyright 2012-2016, Sunny China
8 *                                             All Rights Reserved
9 *
10 * File    : ccu_i.h
11 * By      : Sunny
12 * Version : v1.0
13 * Date    : 2012-5-7
14 * Descript: clock control unit internal header.
15 * Update  : date                auther      ver     notes
16 *           2012-5-7 8:40:42    Sunny       1.0     Create this file.
17 *********************************************************************************************************
18 */
19 
20 #ifndef __CCU_I_H__
21 #define __CCU_I_H__
22 
23 #include "platform.h"
24 #include "ccu_regs.h"
25 
26 #define R_PRCM_REG_BASE SUNXI_R_PRCM_PBASE
27 #define CCU_REG_BASE    SUNXI_CCU_REG_PBASE
28 // prcm regs
29 #define CCU_PLL_CTRL1   (R_PRCM_REG_BASE + 0x244)
30 
31 // name by pll order
32 #define CCU_PLLx_REG(n) (R_PRCM_REG_BASE + 0x1000 + (0x8 * (n - 1)))
33 
34 //name by pll function
35 #define CCU_PLL_C0_REG              (CCU_PLLx_REG(1))
36 #define CCU_PLL_DDR0_REG            (CCU_REG_BASE + 0x800)
37 /* #define CCU_PLL_DDR1_REG            (CCU_PLLx_REG(4)) */
38 #define CCU_PLL_PERIPH0_REG         (CCU_PLLx_REG(3))
39 /* #define CCU_PLL_PERIPH1_REG         (CCU_PLLx_REG(6)) */
40 #define CCU_PLL_VIDEO0_REG          (CCU_PLLx_REG(9))
41 #define CCU_PLL_VIDEO1_REG          (CCU_PLLx_REG(10))
42 #define CCU_PLL_VE_REG              (CCU_PLLx_REG(12))
43 #define CCU_PLL_DE_REG              (CCU_PLLx_REG(13))
44 #define CCU_PLL_HSIC_REG            (CCU_PLLx_REG(15))
45 #define CCU_PLL_AUDIO_REG           (CCU_PLLx_REG(16))
46 #define CCU_CPU_AXI_CFG_REG         (CCU_REG_BASE + 0x500)
47 #define CCU_PSI_AHB1_AHB2_CFG_REG   (CCU_REG_BASE + 0x510)
48 #define CCU_APB1_CFG_REG            (CCU_REG_BASE + 0x520)
49 #define CCU_APB2_CFG_REG            (CCU_REG_BASE + 0x524)
50 #define CCU_CCI_CFG_REG             (CCU_REG_BASE + 0x530)
51 #define CCU_MBUS_CLK_REG            (CCU_REG_BASE + 0x540)
52 #define CCU_MBUS_MASTER_CLK_REG     (CCU_REG_BASE + 0x804)
53 #define CCU_MSGBOX_BGR_REG          (CCU_REG_BASE + 0x71c)
54 #define CCU_SPINLOCK_BGR_REG        (CCU_REG_BASE + 0x72c)
55 #define CCU_DRAM_CLOCK_REG          (CCU_REG_BASE + 0x800)
56 
57 #define CCU_R_AHBS_CFG_REG          (R_PRCM_REG_BASE + 0x0)
58 #define CCU_R_APBS0_CFG_REG         (R_PRCM_REG_BASE + 0xc)
59 #define CCU_R_APBS1_CFG_REG         (R_PRCM_REG_BASE + 0x10)
60 
61 #define CCU_R_LPSD_CLK_REG          (R_PRCM_REG_BASE + 0x0D0)
62 #define CCU_R_MAD_BGR_REG           (R_PRCM_REG_BASE + 0x0DC)
63 #define CCU_R_DMA_BGR_REG           (R_PRCM_REG_BASE + 0x10c)
64 #define CCU_R_AUDIOCODEC_ADC_CLK_REG (R_PRCM_REG_BASE + 0x140)
65 #define CCU_R_AUDIOCODEC_DAC_CLK_REG (R_PRCM_REG_BASE + 0x144)
66 #define CCU_R_AUDIOCODEC_BGR_REG    (R_PRCM_REG_BASE + 0x14C)
67 #define CCU_R_DMIC_CLK_REG          (R_PRCM_REG_BASE + 0x150)
68 #define CCU_R_DMIC_BGR_REG          (R_PRCM_REG_BASE + 0x15C)
69 #define CCU_R_I2S0_CLK_REG          (R_PRCM_REG_BASE + 0x170)
70 #define CCU_R_I2S0_ASRC_CLK_REG     (R_PRCM_REG_BASE + 0x174)
71 #define CCU_R_I2S1_CLK_REG          (R_PRCM_REG_BASE + 0x178)
72 #define CCU_R_I2S_BGR_REG           (R_PRCM_REG_BASE + 0x17C)
73 #define CCU_R_MSGBOX_BGR_REG        (R_PRCM_REG_BASE + 0x1dc)
74 #define R_DSP_BUS_GATING_RESET      (R_PRCM_REG_BASE + 0x1bc)
75 #define VDD_SYS_PWROFF_GATING_REG   (R_PRCM_REG_BASE + 0x250)
76 #define ANALOG_PWROFF_GATING_REG    (R_PRCM_REG_BASE + 0x254)
77 #define DSP_POWER_CONTROL_REG       (R_PRCM_REG_BASE + 0x258)
78 #define VDD_SYS_PWR_RST_REG         (R_PRCM_REG_BASE + 0x260)
79 #define VDD_SYS_DOM_PWR_CTRL_REG    (R_PRCM_REG_BASE + 0x264)
80 #define RES_CAL_CTRL_REG            (R_PRCM_REG_BASE + 0x310)
81 #define BUS_AUTO_CLOCK_GATING_REG   (R_PRCM_REG_BASE + 0x33c)
82 #define MSRAMOC_CTRL_REG            (R_PRCM_REG_BASE + 0x360)
83 
84 #define CCU_PLL_AUDIO0_REG          (R_PRCM_REG_BASE + 0x1020)
85 #define CCU_PLL_AUDIO1_REG          (R_PRCM_REG_BASE + 0x1030)
86 #define CCU_PLL_AUDIO0_PAT0_REG     (R_PRCM_REG_BASE + 0x1120)
87 #define CCU_PLL_AUDIO1_PAT0_REG     (R_PRCM_REG_BASE + 0x1130)
88 
89 #define R_DSP1_DBG_RST_MASK         (1 << 21)
90 #define R_DSP1_DBG_RST(x)           (x << 21)
91 #define R_DSP1_CFG_RST_MASK         (1 << 20)
92 #define R_DSP1_CFG_RST(x)           (x << 20)
93 #define R_DSP1_RST_MASK             (1 << 19)
94 #define R_DSP1_RST(x)               (x << 19)
95 #define R_DSP1_CFG_GATING_MASK      (1 << 3)
96 #define R_DSP1_CFG_GATING(x)        (x << 3)
97 #define R_DSP1_GATING_MASK          (1 << 2)
98 #define R_DSP1_GATING(x)            (x << 2)
99 
100 #define DSP1_POWER_ISOLATION_MASK   (1 << 16)
101 #define DSP1_POWER_ISOLATION(x)     (x << 16)
102 #define DSP1_POWER_SWT_CTL_MASK     (0xff << 8)
103 #define DSP1_POWER_SWT_CTL(x)       (x << 8)
104 #define DSP1_POWER_PWR_STA_MASK     (0xff << 0)
105 
106 #define PLL_NUM     (14)
107 #define BUS_NUM     (10)
108 #define IO_NUM      (2)
109 
110 /* for sun50iw11 pll define */
111 #define CCU_SYS_CLK_CPUX    CCU_SYS_CLK_PLL1
112 #define CCU_SYS_CLK_PERI_1X CCU_SYS_CLK_PLL2
113 #define CCU_SYS_CLK_PERI_2X CCU_SYS_CLK_PLL3
114 #define CCU_SYS_CLK_PERI_800M   CCU_SYS_CLK_PLL4
115 #define CCU_SYS_CLK_AUDIO0_DIV2 CCU_SYS_CLK_PLL5
116 #define CCU_SYS_CLK_AUDIO0_DIV5 CCU_SYS_CLK_PLL6
117 #define CCU_SYS_CLK_AUDIO1_4X   CCU_SYS_CLK_PLL7
118 #define CCU_SYS_CLK_AUDIO1_2X   CCU_SYS_CLK_PLL8
119 #define CCU_SYS_CLK_AUDIO1_1X   CCU_SYS_CLK_AUDIO1
120 
121 #define CCU_AHB1_AHB2_SEL_MASK  (3 << 24)
122 #define CCU_AHB1_AHB2_M_MASK    (3 << 0)
123 #define CCU_AHB1_AHB2_N_MASK    (3 << 8)
124 #define CCU_AHB1_AHB2_SEL_RTC32 (1 << 24)
125 #define CCU_AHB1_AHB2_SEL_24M   (0 << 24)
126 #define CCU_APB1_SEL_MASK       (3 << 24)
127 #define CCU_APB1_SEL_RTC32      (1 << 24)
128 #define CCU_APB1_SEL_24M        (0 << 24)
129 #define CCU_APB1_FACTORN_MASK   (3 << 8)
130 #define CCU_APB1_FACTORM_MASK   (3 << 0)
131 #define CCU_APB2_M_MASK         (3 << 0)
132 #define CCU_APB2_N_MASK         (3 << 8)
133 #define CCU_APB2_SEL_MASK       (3 << 24)
134 #define CCU_APB2_SEL_RTC32      (1 << 24)
135 #define CCU_APB2_SEL_24M        (0 << 24)
136 #define CCU_AXI_SEL_MASK        (7 << 24)
137 #define CCU_AXI_SEL_24M         (0 << 24)
138 #define CCU_AXI_SEL_RTC32       (1 << 24)
139 #define CCU_AXI_FACTOR_M_MASK   (3 << 0)
140 #define CCU_AXI_APB_N_MASK      (3 << 8)
141 #define CCU_AXI_SRC_SEL_MASK    (7 << 24)
142 
143 #define CPUX_PLL_ENABLE_MASK    (1 << 31)
144 #define CPUX_PLL_ENABLE         (1 << 31)
145 #define CPUX_PLL_DISABLE        (0 << 31)
146 #define CPUX_PLL_LOCK_MASK      (1 << 29)
147 #define CPUX_PLL_LOCK_ENABLE    (1 << 29)
148 #define CPUX_PLL_LOCK_DISABLE   (1 << 29)
149 #define CPUX_PLL_LOCK_STATUS    (1 << 28)
150 
151 #define VDD_SYS_GATING_MASK (3 << 0)
152 #define VDD_SYS_GATING      (3 << 0)
153 #define VDD_SYS_NOT_GATING  (0 << 0)
154 
155 #define ANALOG_PWROFF_GATING_MASK (1 << 0)
156 #define ANALOG_PWROFF_GATING      (1 << 0)
157 #define ANALOG_PWROFF_NOT_GATING  (0 << 0)
158 
159 #define VDD_SYS_PWR_RST_MASK      (1 << 0)
160 #define VDD_SYS_PWR_RST_ASSERT    (0 << 0)
161 #define VDD_SYS_PWR_RST_DEASSERT  (1 << 0)
162 
163 #define MSRAMOC_PORT_HOLD_EN      (1 << 1)
164 #define MSRAMOC_ACG_EN            (1 << 0)
165 #define AHBS_AUTO_CLK_GATE_EN     (1 << 24)
166 #define BM_ACG_MODE_EN            (1 << 0)
167 
168 
169 #define CCU_R_APBSx_SEL_MASK    (0x7<<24)
170 #define CCU_R_APBSx_SEL_DCXO24M          (0x0<<24)
171 #define CCU_R_APBSx_SEL_RTC32K           (0x1<<24)
172 #define CCU_R_APBSx_SEL_RC16M            (0x2<<24)
173 #define CCU_R_APBSx_SEL_PLL_PERI2X       (0x3<<24)
174 #define CCU_R_APBSx_SEL_PLL_AUDIO0DIV2   (0x4<<24)
175 
176 typedef struct ccu_pll1_factor {
177     u8 factor_n;
178     u8 factor_k;
179     u8 factor_m;
180     u8 factor_p;
181     u32 freq;
182 } ccu_pll1_factor_t;
183 
184 /* local functions */
185 s32 ccu_set_cpus_src(u32 sclk);
186 
187 /* ccu module registers address */
188 extern struct ccu_reg_list *ccu_reg_addr;
189 extern struct ccu_pll_c0_cpux_reg0000 *ccu_pll_c0_cpux_reg_addr;
190 extern struct ccu_pll_ddr0_reg0010 *ccu_pll_ddr0_reg_addr;
191 extern struct ccu_pll_periph_reg0010 *ccu_pll_periph0_reg_addr;
192 extern struct ccu_pll_audio0_reg0020 *ccu_pll_audio0_reg_addr;
193 extern struct ccu_pll_periph1_reg0028 *ccu_pll_periph1_reg_addr;
194 
195 /* apb notifier list */
196 extern struct notifier *apbs2_notifier_head;
197 
198 #endif /* __CCU_I_H__ */
199