1 /***************COPYRIGHT(C) 2019 WCH. A11 rights reserved********************* 2 * File Name : ch32f10x_dma.h 3 * Author : WCH 4 * Version : V1.0.0 5 * Date : 2019/10/15 6 * Description : This file contains all the functions prototypes for the 7 * DMA firmware library. 8 *******************************************************************************/ 9 #ifndef __CH32F10x_DMA_H 10 #define __CH32F10x_DMA_H 11 12 #ifdef __cplusplus 13 extern "C" { 14 #endif 15 16 #include "ch32f10x.h" 17 18 /* DMA Init structure definition */ 19 typedef struct 20 { 21 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ 22 23 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ 24 25 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. 26 This parameter can be a value of @ref DMA_data_transfer_direction */ 27 28 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. 29 The data unit is equal to the configuration set in DMA_PeripheralDataSize 30 or DMA_MemoryDataSize members depending in the transfer direction. */ 31 32 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. 33 This parameter can be a value of @ref DMA_peripheral_incremented_mode */ 34 35 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. 36 This parameter can be a value of @ref DMA_memory_incremented_mode */ 37 38 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. 39 This parameter can be a value of @ref DMA_peripheral_data_size */ 40 41 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. 42 This parameter can be a value of @ref DMA_memory_data_size */ 43 44 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. 45 This parameter can be a value of @ref DMA_circular_normal_mode. 46 @note: The circular buffer mode cannot be used if the memory-to-memory 47 data transfer is configured on the selected Channel */ 48 49 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. 50 This parameter can be a value of @ref DMA_priority_level */ 51 52 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. 53 This parameter can be a value of @ref DMA_memory_to_memory */ 54 }DMA_InitTypeDef; 55 56 /* DMA_data_transfer_direction */ 57 #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) 58 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) 59 60 /* DMA_peripheral_incremented_mode */ 61 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) 62 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) 63 64 /* DMA_memory_incremented_mode */ 65 #define DMA_MemoryInc_Enable ((uint32_t)0x00000080) 66 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) 67 68 /* DMA_peripheral_data_size */ 69 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) 70 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) 71 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) 72 73 /* DMA_memory_data_size */ 74 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) 75 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) 76 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) 77 78 /* DMA_circular_normal_mode */ 79 #define DMA_Mode_Circular ((uint32_t)0x00000020) 80 #define DMA_Mode_Normal ((uint32_t)0x00000000) 81 82 /* DMA_priority_level */ 83 #define DMA_Priority_VeryHigh ((uint32_t)0x00003000) 84 #define DMA_Priority_High ((uint32_t)0x00002000) 85 #define DMA_Priority_Medium ((uint32_t)0x00001000) 86 #define DMA_Priority_Low ((uint32_t)0x00000000) 87 88 /* DMA_memory_to_memory */ 89 #define DMA_M2M_Enable ((uint32_t)0x00004000) 90 #define DMA_M2M_Disable ((uint32_t)0x00000000) 91 92 /* DMA_interrupts_definition */ 93 #define DMA_IT_TC ((uint32_t)0x00000002) 94 #define DMA_IT_HT ((uint32_t)0x00000004) 95 #define DMA_IT_TE ((uint32_t)0x00000008) 96 97 #define DMA1_IT_GL1 ((uint32_t)0x00000001) 98 #define DMA1_IT_TC1 ((uint32_t)0x00000002) 99 #define DMA1_IT_HT1 ((uint32_t)0x00000004) 100 #define DMA1_IT_TE1 ((uint32_t)0x00000008) 101 #define DMA1_IT_GL2 ((uint32_t)0x00000010) 102 #define DMA1_IT_TC2 ((uint32_t)0x00000020) 103 #define DMA1_IT_HT2 ((uint32_t)0x00000040) 104 #define DMA1_IT_TE2 ((uint32_t)0x00000080) 105 #define DMA1_IT_GL3 ((uint32_t)0x00000100) 106 #define DMA1_IT_TC3 ((uint32_t)0x00000200) 107 #define DMA1_IT_HT3 ((uint32_t)0x00000400) 108 #define DMA1_IT_TE3 ((uint32_t)0x00000800) 109 #define DMA1_IT_GL4 ((uint32_t)0x00001000) 110 #define DMA1_IT_TC4 ((uint32_t)0x00002000) 111 #define DMA1_IT_HT4 ((uint32_t)0x00004000) 112 #define DMA1_IT_TE4 ((uint32_t)0x00008000) 113 #define DMA1_IT_GL5 ((uint32_t)0x00010000) 114 #define DMA1_IT_TC5 ((uint32_t)0x00020000) 115 #define DMA1_IT_HT5 ((uint32_t)0x00040000) 116 #define DMA1_IT_TE5 ((uint32_t)0x00080000) 117 #define DMA1_IT_GL6 ((uint32_t)0x00100000) 118 #define DMA1_IT_TC6 ((uint32_t)0x00200000) 119 #define DMA1_IT_HT6 ((uint32_t)0x00400000) 120 #define DMA1_IT_TE6 ((uint32_t)0x00800000) 121 #define DMA1_IT_GL7 ((uint32_t)0x01000000) 122 #define DMA1_IT_TC7 ((uint32_t)0x02000000) 123 #define DMA1_IT_HT7 ((uint32_t)0x04000000) 124 #define DMA1_IT_TE7 ((uint32_t)0x08000000) 125 126 #define DMA2_IT_GL1 ((uint32_t)0x10000001) 127 #define DMA2_IT_TC1 ((uint32_t)0x10000002) 128 #define DMA2_IT_HT1 ((uint32_t)0x10000004) 129 #define DMA2_IT_TE1 ((uint32_t)0x10000008) 130 #define DMA2_IT_GL2 ((uint32_t)0x10000010) 131 #define DMA2_IT_TC2 ((uint32_t)0x10000020) 132 #define DMA2_IT_HT2 ((uint32_t)0x10000040) 133 #define DMA2_IT_TE2 ((uint32_t)0x10000080) 134 #define DMA2_IT_GL3 ((uint32_t)0x10000100) 135 #define DMA2_IT_TC3 ((uint32_t)0x10000200) 136 #define DMA2_IT_HT3 ((uint32_t)0x10000400) 137 #define DMA2_IT_TE3 ((uint32_t)0x10000800) 138 #define DMA2_IT_GL4 ((uint32_t)0x10001000) 139 #define DMA2_IT_TC4 ((uint32_t)0x10002000) 140 #define DMA2_IT_HT4 ((uint32_t)0x10004000) 141 #define DMA2_IT_TE4 ((uint32_t)0x10008000) 142 #define DMA2_IT_GL5 ((uint32_t)0x10010000) 143 #define DMA2_IT_TC5 ((uint32_t)0x10020000) 144 #define DMA2_IT_HT5 ((uint32_t)0x10040000) 145 #define DMA2_IT_TE5 ((uint32_t)0x10080000) 146 147 /* DMA_flags_definition */ 148 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) 149 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) 150 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) 151 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) 152 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) 153 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) 154 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) 155 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) 156 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) 157 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) 158 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) 159 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) 160 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) 161 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) 162 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) 163 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) 164 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) 165 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) 166 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) 167 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) 168 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) 169 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) 170 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) 171 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) 172 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) 173 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) 174 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) 175 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) 176 177 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001) 178 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002) 179 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004) 180 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008) 181 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010) 182 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020) 183 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040) 184 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080) 185 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100) 186 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200) 187 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400) 188 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800) 189 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000) 190 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000) 191 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000) 192 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000) 193 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000) 194 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000) 195 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000) 196 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000) 197 198 /* DMA_Exported_Functions */ 199 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); 200 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); 201 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); 202 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); 203 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); 204 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 205 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); 206 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); 207 void DMA_ClearFlag(uint32_t DMAy_FLAG); 208 ITStatus DMA_GetITStatus(uint32_t DMAy_IT); 209 void DMA_ClearITPendingBit(uint32_t DMAy_IT); 210 211 #ifdef __cplusplus 212 } 213 #endif 214 215 #endif /*__CH32F10x_DMA_H */ 216 217