1 /***************COPYRIGHT(C)  2019 WCH. A11 rights reserved*********************
2 * File Name          : ch32f10x_rcc.h
3 * Author             : WCH
4 * Version            : V1.0.0
5 * Date               : 2019/10/15
6 * Description        : This file provides all the RCC firmware functions.
7 *******************************************************************************/
8 #ifndef __CH32F10x_RCC_H
9 #define __CH32F10x_RCC_H
10 
11 #ifdef __cplusplus
12  extern "C" {
13 #endif
14 
15 #include "ch32f10x.h"
16 
17 /* RCC_Exported_Types */
18 typedef struct
19 {
20   uint32_t SYSCLK_Frequency;  /*!< returns SYSCLK clock frequency expressed in Hz */
21   uint32_t HCLK_Frequency;    /*!< returns HCLK clock frequency expressed in Hz */
22   uint32_t PCLK1_Frequency;   /*!< returns PCLK1 clock frequency expressed in Hz */
23   uint32_t PCLK2_Frequency;   /*!< returns PCLK2 clock frequency expressed in Hz */
24   uint32_t ADCCLK_Frequency;  /*!< returns ADCCLK clock frequency expressed in Hz */
25 }RCC_ClocksTypeDef;
26 
27 /* HSE_configuration */
28 #define RCC_HSE_OFF                      ((uint32_t)0x00000000)
29 #define RCC_HSE_ON                       ((uint32_t)0x00010000)
30 #define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
31 
32 /* PLL_entry_clock_source */
33 #define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
34 #define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
35 #define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
36 
37 /* PLL_multiplication_factor */
38 #define RCC_PLLMul_2                     ((uint32_t)0x00000000)
39 #define RCC_PLLMul_3                     ((uint32_t)0x00040000)
40 #define RCC_PLLMul_4                     ((uint32_t)0x00080000)
41 #define RCC_PLLMul_5                     ((uint32_t)0x000C0000)
42 #define RCC_PLLMul_6                     ((uint32_t)0x00100000)
43 #define RCC_PLLMul_7                     ((uint32_t)0x00140000)
44 #define RCC_PLLMul_8                     ((uint32_t)0x00180000)
45 #define RCC_PLLMul_9                     ((uint32_t)0x001C0000)
46 #define RCC_PLLMul_10                    ((uint32_t)0x00200000)
47 #define RCC_PLLMul_11                    ((uint32_t)0x00240000)
48 #define RCC_PLLMul_12                    ((uint32_t)0x00280000)
49 #define RCC_PLLMul_13                    ((uint32_t)0x002C0000)
50 #define RCC_PLLMul_14                    ((uint32_t)0x00300000)
51 #define RCC_PLLMul_15                    ((uint32_t)0x00340000)
52 #define RCC_PLLMul_16                    ((uint32_t)0x00380000)
53 
54 /* System_clock_source */
55 #define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
56 #define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
57 #define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
58 
59 /* AHB_clock_source */
60 #define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
61 #define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
62 #define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
63 #define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
64 #define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
65 #define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
66 #define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
67 #define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
68 #define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
69 
70 /* APB1_APB2_clock_source */
71 #define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
72 #define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
73 #define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
74 #define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
75 #define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
76 
77 /* RCC_Interrupt_source */
78 #define RCC_IT_LSIRDY                    ((uint8_t)0x01)
79 #define RCC_IT_LSERDY                    ((uint8_t)0x02)
80 #define RCC_IT_HSIRDY                    ((uint8_t)0x04)
81 #define RCC_IT_HSERDY                    ((uint8_t)0x08)
82 #define RCC_IT_PLLRDY                    ((uint8_t)0x10)
83 #define RCC_IT_CSS                       ((uint8_t)0x80)
84 
85 /* USB_Device_clock_source */
86 #define RCC_USBCLKSource_PLLCLK_1Div5    ((uint8_t)0x00)
87 #define RCC_USBCLKSource_PLLCLK_Div1     ((uint8_t)0x01)
88 
89 /* ADC_clock_source */
90 #define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
91 #define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
92 #define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
93 #define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
94 
95 /* LSE_configuration */
96 #define RCC_LSE_OFF                      ((uint8_t)0x00)
97 #define RCC_LSE_ON                       ((uint8_t)0x01)
98 #define RCC_LSE_Bypass                   ((uint8_t)0x04)
99 
100 /* RTC_clock_source */
101 #define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
102 #define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
103 #define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
104 
105 /* AHB_peripheral */
106 #define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
107 #define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
108 #define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
109 #define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
110 #define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
111 #define RCC_AHBPeriph_FSMC               ((uint32_t)0x00000100)
112 #define RCC_AHBPeriph_SDIO               ((uint32_t)0x00000400)
113 
114 /* APB2_peripheral */
115 #define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
116 #define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
117 #define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
118 #define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
119 #define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
120 #define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
121 #define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
122 #define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
123 #define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
124 #define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
125 #define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
126 #define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
127 #define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
128 #define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
129 #define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
130 #define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
131 #define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
132 #define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
133 #define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
134 #define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
135 #define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
136 
137 /* APB1_peripheral */
138 #define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
139 #define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
140 #define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
141 #define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
142 #define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
143 #define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
144 #define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
145 #define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
146 #define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
147 #define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
148 #define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
149 #define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
150 #define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
151 #define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
152 #define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
153 #define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
154 #define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
155 #define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
156 #define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
157 #define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
158 #define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
159 #define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
160 #define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
161 #define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
162 #define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
163 
164 /* Clock_source_to_output_on_MCO_pin */
165 #define RCC_MCO_NoClock                  ((uint8_t)0x00)
166 #define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
167 #define RCC_MCO_HSI                      ((uint8_t)0x05)
168 #define RCC_MCO_HSE                      ((uint8_t)0x06)
169 #define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
170 
171 /* RCC_Flag */
172 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
173 #define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
174 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
175 #define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
176 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
177 #define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
178 #define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
179 #define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
180 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
181 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
182 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
183 
184 
185 void RCC_DeInit(void);
186 void RCC_HSEConfig(uint32_t RCC_HSE);
187 ErrorStatus RCC_WaitForHSEStartUp(void);
188 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
189 void RCC_HSICmd(FunctionalState NewState);
190 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
191 void RCC_PLLCmd(FunctionalState NewState);
192 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
193 uint8_t RCC_GetSYSCLKSource(void);
194 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
195 void RCC_PCLK1Config(uint32_t RCC_HCLK);
196 void RCC_PCLK2Config(uint32_t RCC_HCLK);
197 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
198 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
199 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
200 void RCC_LSEConfig(uint8_t RCC_LSE);
201 void RCC_LSICmd(FunctionalState NewState);
202 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
203 void RCC_RTCCLKCmd(FunctionalState NewState);
204 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
205 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
206 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
207 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
208 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
209 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
210 void RCC_BackupResetCmd(FunctionalState NewState);
211 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
212 void RCC_MCOConfig(uint8_t RCC_MCO);
213 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
214 void RCC_ClearFlag(void);
215 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
216 void RCC_ClearITPendingBit(uint8_t RCC_IT);
217 
218 #ifdef __cplusplus
219 }
220 #endif
221 
222 #endif /* __CH32F10x_RCC_H */
223 
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