1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-07-15 Emuzit first version 9 */ 10 #ifndef __CH56X_GPIO_H__ 11 #define __CH56X_GPIO_H__ 12 13 #include "soc.h" 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 /* Fixed linear mapping : 32 pins per port, for ports A,B,C,D... 20 */ 21 #define GET_PIN(port,pin) (GPIO_P##port##_PIN_START + pin) 22 23 #ifdef SOC_SERIES_CH569 24 #define GPIO_INT_PINS { \ 25 GET_PIN(A,2), GET_PIN(A,3), GET_PIN(A,4), GET_PIN(B,3), \ 26 GET_PIN(B,4), GET_PIN(B,11), GET_PIN(B,12), GET_PIN(B,15) \ 27 } 28 #else 29 #define GPIO_INT_PINS { \ 30 GET_PIN(A,3), GET_PIN(A,4), GET_PIN(A,6), GET_PIN(A,10), \ 31 GET_PIN(A,11), GET_PIN(A,12), GET_PIN(B,4), GET_PIN(B,10), \ 32 } 33 #endif 34 35 /* 36 * R8_GPIO_INT_FLAG / R8_GPIO_INT_STATUS (CH567,CH568): 37 * write 1 to specific bit to clear int flag 38 * 39 * R8_GPIO_INT_ENABLE: 40 * To use EXTIx function, pin should be set as input. 41 * For wakeup function, also set RB_SLP_GPIO_WAKE. 42 * 43 * R8_GPIO_INT_MODE: 44 * R8_GPIO_INT_POLAR: 45 */ 46 #if defined(SOC_SERIES_CH569) 47 union _gpio_interrupt 48 { 49 uint8_t reg; 50 struct 51 { 52 uint8_t pa2 : 1; 53 uint8_t pa3 : 1; 54 uint8_t pa4 : 1; 55 uint8_t pb3 : 1; 56 uint8_t pb4 : 1; 57 uint8_t pb11 : 1; 58 uint8_t pb12 : 1; 59 uint8_t pb15 : 1; 60 }; 61 }; 62 63 #else 64 65 union _gpio_interrupt 66 { 67 uint8_t reg; 68 struct 69 { 70 uint8_t pa3 : 1; 71 uint8_t pa4 : 1; 72 uint8_t pa6 : 1; 73 uint8_t pa10 : 1; 74 uint8_t pa11 : 1; 75 uint8_t pa12 : 1; 76 uint8_t pb4 : 1; 77 uint8_t pb10 : 1; 78 }; 79 }; 80 #endif 81 82 #define GPIO_IE_DISABLE 0 83 #define GPIO_IE_ENABLE 1 84 85 #define GPIO_IM_LEVEL 0 86 #define GPIO_IM_EDGE 1 87 88 #define GPIO_IP_LOW_FALLING 0 89 #define GPIO_IP_HIGH_RISING 1 90 91 /* 92 * R8_PIN_ALTERNATE (CH569) : reset value is 0x01 93 * R8_PORT_PIN (CH567/CH568) : reset value is 0x00 94 */ 95 union _gpio_pin_alternate 96 { 97 uint8_t reg; 98 struct 99 { 100 uint8_t pin_mii : 1; // RW, ETH uses RMII/RGMII (CH565W/CH569W) 101 uint8_t pin_tmr1 : 1; // RW, TMR1/PWM5/CAP1 remapping 102 uint8_t pin_tmr2 : 1; // RW, TMR2/PWM6/CAP2 remapping 103 uint8_t resv_3 : 1; 104 uint8_t pin_uart0 : 1; // RW, RXD0/TXD0 remapping 105 uint8_t pin_uart1 : 1; // RW, CH567 only 106 uint8_t resv_6 : 2; 107 }; 108 }; 109 #define RB_PIN_MII 0x01 110 #define RB_PIN_TMR1 0x02 111 #define RB_PIN_TMR2 0x04 112 #define RB_PIN_UART0 0x10 113 #define RB_PIN_UART1 0x20 114 115 #ifdef SOC_SERIES_CH569 116 #define GPIO_ALT_RMII 0 117 #define GPIO_ALT_RGMII 1 118 #define GPIO_ALT_TMR1_PB15 0 119 #define GPIO_ALT_TMR1_PB0 1 120 #define GPIO_ALT_TMR2_PA4 0 121 #define GPIO_ALT_TMR2_PB3 1 122 #define GPIO_ALT_UART0_PB5_6 0 123 #define GPIO_ALT_UART0_PA5_6 1 124 #else 125 #define GPIO_ALT_TMR1_PA10 0 126 #define GPIO_ALT_TMR1_PB2 1 127 #define GPIO_ALT_TMR2_PA11 0 128 #define GPIO_ALT_TMR2_PB11 1 129 #define GPIO_ALT_UART0_PB4_7 0 130 #define GPIO_ALT_UART0_PA15_14 1 131 #define GPIO_ALT_UART1_PA8_9 0 132 #define GPIO_ALT_UART1_PB8_9 1 133 #endif 134 135 struct gpio_px_regs 136 { 137 uint32_t DIR; // reset value for pins is 0, input pins 138 uint32_t PIN; // RO 139 uint32_t OUT; // reset value is 0 140 uint32_t CLR; // reset value is 0 141 uint32_t PU; // reset value is 0 142 uint32_t PD; // reset value is 0 143 uint32_t DRV; // reset value for pins is 0, 8mA 144 uint32_t SMT; // reset value for pins is 1, enable schmitt trigger 145 } __packed; 146 147 CHECK_STRUCT_SIZE(struct gpio_px_regs, 0x20); 148 149 #define GPIO_PX_DIR_IN 0 150 #define GPIO_PX_DIR_OUT 1 151 152 #define GPIO_PX_PU_DISABLE 0 153 #define GPIO_PX_PU_ENABLE 1 154 #define GPIO_PX_PD_DISABLE 0 // for DIR_IN 155 #define GPIO_PX_PD_ENABLE 1 // for DIR_IN 156 #define GPIO_PX_PD_PUSH_PULL 0 // for DIR_OUT 157 #define GPIO_PX_PD_OPEN_DRAIN 1 // for DIR_OUT 158 159 #define GPIO_PX_DRV_8mA 0 160 #define GPIO_PX_DRV_16mA 1 161 162 #define GPIO_PX_SMT_DISABLE 0 163 #define GPIO_PX_SMT_SLOW 1 // for DIR_OUT 164 #define GPIO_PX_SMT_ENABLE 1 // for DIR_IN 165 166 /* 167 * 0x12 R8_PIN_ALTERNATE: GPIO multi-use remapping register 168 * 0x1c R8_GPIO_INT_FLAG: GPIO interrupt flag register 169 * 0x1d R8_GPIO_INT_ENABLE: GPIO interrupt enable register 170 * 0x1e R8_GPIO_INT_MODE: GPIO interrupt mode register 171 * 0x1f R8_GPIO_INT_POLAR: GPIO interrupt polarity register 172 * 173 * 0x40 R32_PA_DIR: PA pin direction control 174 * 0x44 R32_PA_PIN: PA pin input status 175 * 0x48 R32_PA_OUT: PA pin output register 176 * 0x4c R32_PA_CLR: PA pin output clear 177 * 0x50 R32_PA_PU: PA pin pull-up resistor enable register 178 * 0x54 R32_PA_PD: PA pin open drain output / input pull-down control 179 * 0x58 R32_PA_DRV: PA pin output driving capability register 180 * 0x5c R32_PA_SMT: PA pin slow output / schmitt trigger input control 181 * 182 * 0x60 R32_PB_DIR: 183 * 0x64 R32_PB_PIN: 184 * 0x68 R32_PB_OUT: 185 * 0x6c R32_PB_CLR: 186 * 0x70 R32_PB_PU: 187 * 0x74 R32_PB_PD: 188 * 0x78 R32_PB_DRV: 189 * 0x7c R32_PB_SMT: 190 * 191 * CAVEAT: gcc (as of 8.2.0) tends to read 32-bit word for bit field test. 192 * Be careful for those with side effect for read. 193 */ 194 struct gpio_registers 195 { 196 uint32_t resv_00[4]; 197 uint8_t resv_10[2]; 198 union _gpio_pin_alternate PIN_ALTERNATE; 199 uint8_t resv_13; 200 uint32_t resv_14[2]; 201 union _gpio_interrupt INT_FLAG; 202 union _gpio_interrupt INT_ENABLE; 203 union _gpio_interrupt INT_MODE; 204 union _gpio_interrupt INT_POLAR; 205 uint32_t resv_20[8]; 206 struct gpio_px_regs PA; 207 struct gpio_px_regs PB; 208 } __packed; 209 210 CHECK_STRUCT_SIZE(struct gpio_registers, 0x80); 211 212 #ifdef __cplusplus 213 } 214 #endif 215 216 #endif 217