1 /*
2  * Copyright (c) 2006-2023, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author            Notes
8  * 2022-08-04     Emuzit            first version
9  */
10 #ifndef __CH56X_PWM_H__
11 #define __CH56X_PWM_H__
12 
13 #include "soc.h"
14 #include "ch56x_gpio.h"
15 
16 #ifdef __cplusplus
17 extern "C" {
18 #endif
19 
20 #define PWM_DEVICE_NAME     "pwmx"
21 
22 #define PWM_CHANNELS        4
23 
24 #define PWM0_PIN            GET_PIN(B, 15)
25 #define PWM1_PIN            GET_PIN(A, 4)
26 #define PWM2_PIN            GET_PIN(B, 1)
27 #define PWM3_PIN            GET_PIN(B, 2)
28 
29 union _pwm_ctrl_mod
30 {
31     uint8_t reg;
32     struct
33     {
34         uint8_t pwm0_out_en : 1;  // RW, PWM output enable
35         uint8_t pwm1_out_en : 1;
36         uint8_t pwm2_out_en : 1;
37         uint8_t pwm3_out_en : 1;
38         uint8_t pwm0_polar  : 1;  // RW, PWM output polarity
39         uint8_t pwm1_polar  : 1;
40         uint8_t pwm2_polar  : 1;
41         uint8_t pwm3_polar  : 1;
42     };
43 };
44 #define RB_PWM0_OUT_EN      0x01
45 #define RB_PWM1_OUT_EN      0x02
46 #define RB_PWM2_OUT_EN      0x04
47 #define RB_PWM3_OUT_EN      0x08
48 #define RB_PWM0_POLAR       0x10
49 #define RB_PWM1_POLAR       0x20
50 #define RB_PWM2_POLAR       0x40
51 #define RB_PWM3_POLAR       0x80
52 
53 #define PWM_OUT_EN_MASK     0x0f
54 
55 union _pwm_ctrl_cfg
56 {
57     uint8_t reg;
58     struct
59     {
60         uint8_t cycle_sel   : 1;  // RW, PWM cycle select, 0/1 for 256/255
61         uint8_t resv_1      : 7;
62     };
63 };
64 #define RB_PWM_CYCLE_SEL    0x01
65 
66 #define PWM_CYCLE_SEL_256   0
67 #define PWM_CYCLE_SEL_255   1
68 
69 /*
70  * 0x00  R8_PWM_CTRL_MOD:   PWM control register
71  * 0x01  R8_PWM_CTRL_CFG:   PWM control configuration register
72  * 0x02  R8_PWM_CLOCK_DIV:  PWM clock divisor register
73  * 0x04  R8_PWM0_DATA:      PWM0 data holding register
74  * 0x05  R8_PWM1_DATA:      PWM1 data holding register
75  * 0x06  R8_PWM2_DATA:      PWM2 data holding register
76  * 0x07  R8_PWM3_DATA:      PWM3 data holding register
77  */
78 struct pwm_registers
79 {
80     union _pwm_ctrl_mod     CTRL_MOD;
81     union _pwm_ctrl_cfg     CTRL_CFG;
82     uint8_t                 CLOCK_DIV;
83     uint8_t                 resv_3;
84     union
85     {
86         uint32_t            R32_PWM_DATA;
87         uint8_t             PWM_DATA[4];
88         struct
89         {
90             uint8_t         PWM0_DATA;
91             uint8_t         PWM1_DATA;
92             uint8_t         PWM2_DATA;
93             uint8_t         PWM3_DATA;
94         };
95     };
96 };
97 CHECK_STRUCT_SIZE(struct pwm_registers, 8);
98 
99 #ifdef __cplusplus
100 }
101 #endif
102 
103 #endif
104