1 /* 2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2020-08-20 zx.chen header file for usart driver 9 */ 10 11 #ifndef __CK_USART_H 12 #define __CK_USART_H 13 14 #include <stdio.h> 15 #include "errno.h" 16 #include "soc.h" 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #define BAUDRATE_DEFAULT 19200 23 #define UART_BUSY_TIMEOUT 1000000 24 #define UART_RECEIVE_TIMEOUT 1000 25 #define UART_TRANSMIT_TIMEOUT 1000 26 #define UART_MAX_FIFO 0x10 27 /* UART register bit definitions */ 28 29 #define USR_UART_BUSY 0x01 30 #define USR_UART_TFE 0x04 31 #define USR_UART_RFNE 0x08 32 #define LSR_DATA_READY 0x01 33 #define LSR_THR_EMPTY 0x20 34 #define IER_RDA_INT_ENABLE 0x01 35 #define IER_THRE_INT_ENABLE 0x02 36 #define IIR_RECV_LINE_ENABLE 0x04 37 #define IIR_NO_ISQ_PEND 0x01 38 39 #define LCR_SET_DLAB 0x80 /* enable r/w DLR to set the baud rate */ 40 #define LCR_PARITY_ENABLE 0x08 /* parity enabled */ 41 #define LCR_PARITY_EVEN 0x10 /* Even parity enabled */ 42 #define LCR_PARITY_ODD 0xef /* Odd parity enabled */ 43 #define LCR_WORD_SIZE_5 0xfc /* the data length is 5 bits */ 44 #define LCR_WORD_SIZE_6 0x01 /* the data length is 6 bits */ 45 #define LCR_WORD_SIZE_7 0x02 /* the data length is 7 bits */ 46 #define LCR_WORD_SIZE_8 0x03 /* the data length is 8 bits */ 47 #define LCR_STOP_BIT1 0xfb /* 1 stop bit */ 48 #define LCR_STOP_BIT2 0x04 /* 1.5 stop bit */ 49 50 #define DW_LSR_PFE 0x80 51 #define DW_LSR_TEMT 0x40 52 #define DW_LSR_THRE 0x40 53 #define DW_LSR_BI 0x10 54 #define DW_LSR_FE 0x08 55 #define DW_LSR_PE 0x04 56 #define DW_LSR_OE 0x02 57 #define DW_LSR_DR 0x01 58 #define DW_LSR_TRANS_EMPTY 0x20 59 60 #define DW_IIR_THR_EMPTY 0x02 /* threshold empty */ 61 #define DW_IIR_RECV_DATA 0x04 /* received data available */ 62 #define DW_IIR_RECV_LINE 0x06 /* receiver line status */ 63 #define DW_IIR_CHAR_TIMEOUT 0x0c /* character timeout */ 64 65 typedef struct 66 { 67 union 68 { 69 __IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */ 70 __OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */ 71 __IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */ 72 }; 73 union 74 { 75 __IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */ 76 __IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */ 77 }; 78 __IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt indicia register */ 79 __IOM uint32_t LCR; /* Offset: 0x00C (R/W) Transmission control register */ 80 uint32_t RESERVED0; 81 __IM uint32_t LSR; /* Offset: 0x014 (R/ ) Transmission state register */ 82 __IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */ 83 uint32_t RESERVED1[24]; 84 __IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */ 85 } ck_usart_reg_t; 86 87 #ifdef __cplusplus 88 } 89 #endif 90 91 #endif /* __CK_USART_H */ 92 93