1 //***************************************************************************** 2 // 3 // Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ 4 // 5 // Redistribution and use in source and binary forms, with or without 6 // modification, are permitted provided that the following conditions 7 // are met: 8 // 9 // Redistributions of source code must retain the above copyright 10 // notice, this list of conditions and the following disclaimer. 11 // 12 // Redistributions in binary form must reproduce the above copyright 13 // notice, this list of conditions and the following disclaimer in the 14 // documentation and/or other materials provided with the 15 // distribution. 16 // 17 // Neither the name of Texas Instruments Incorporated nor the names of 18 // its contributors may be used to endorse or promote products derived 19 // from this software without specific prior written permission. 20 // 21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 // 33 // MSP432 Family CMSIS Definitions 34 // 35 //**************************************************************************** 36 37 #ifndef CMSIS_CCS_H_ 38 #define CMSIS_CCS_H_ 39 40 #ifndef __TI_ARM__ 41 #error This file should only be compiled by TI compiler (minimum version 15.12.x) 42 #endif 43 44 /** CMSIS compiler control architecture macros */ 45 #if defined ( __TI_ARM_V6M0__ ) 46 #define __ARM_ARCH_6M__ 1 47 #endif 48 49 #if defined ( __TI_ARM_V7M3__ ) 50 #define __ARM_ARCH_7M__ 1 51 #endif 52 53 #if defined ( __TI_ARM_V7M4__ ) 54 #define __ARM_ARCH_7EM__ 1 55 #endif 56 57 /* ########################### Core Function Access ########################### */ 58 /** \ingroup CMSIS_Core_FunctionInterface 59 * \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 60 * @{ 61 */ 62 63 /** 64 * \brief Enable IRQ Interrupts 65 * \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 66 * Can only be executed in Privileged modes. 67 */ 68 #define __enable_irq _enable_IRQ 69 70 /** 71 * \brief Disable IRQ Interrupts 72 * \details Disables IRQ interrupts by setting the I-bit in the CPSR. 73 * Can only be executed in Privileged modes. 74 */ 75 #define __disable_irq _disable_IRQ 76 77 /** @} */ /* end of CMSIS_Core_RegAccFunctions */ 78 79 /* ########################## Core Instruction Access ######################### */ 80 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 81 * Access to dedicated instructions 82 * @{ 83 */ 84 85 /** 86 * \brief Count leading zeros 87 * \details Counts the number of leading zeros of a data value. 88 * \param [in] VAL Value to count the leading zeros 89 * \return number of leading zeros in value 90 */ 91 #define __CLZ(VAL) ((unsigned char)__clz(VAL)) 92 93 /** 94 * \brief Signed Saturate 95 * \details Saturates a signed value. 96 * \param [in] VAL Value to be saturated 97 * \param [in] BITPOS Bit position to saturate to (1..32) 98 * \return Saturated value 99 */ 100 #define __SSAT(VAL, BITPOS) _ssatl(VAL, 0, BITPOS) 101 102 /** 103 * \brief No Operation 104 * \details No Operation does nothing. This instruction can be used for code alignment purposes. 105 */ 106 #define __NOP __nop 107 108 /** 109 * \brief Wait For Interrupt 110 * \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. 111 */ 112 #define __WFI __wfi 113 114 115 /** 116 * \brief Wait For Event 117 * \details Wait For Event is a hint instruction that permits the processor to enter 118 * a low-power state until one of a number of events occurs. 119 */ 120 #define __WFE __wfe 121 122 /** 123 * \brief Data Synchronization Barrier 124 * \details Acts as a special kind of Data Memory Barrier. 125 * It completes when all explicit memory accesses before this instruction complete. 126 */ 127 128 #define __DSB _dsb 129 /** 130 * \brief Instruction Synchronization Barrier 131 * \details Instruction Synchronization Barrier flushes the pipeline in the processor, 132 * so that all instructions following the ISB are fetched from cache or memory, 133 * after the instruction has been completed. 134 */ 135 #define __ISB _isb 136 137 /** 138 \brief Data Memory Barrier 139 \details Ensures the apparent order of the explicit memory operations before 140 and after the instruction, without ensuring their completion. 141 */ 142 #define __DMB _dmb 143 /** 144 * \brief Rotate Right in unsigned value (32 bit) 145 * \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 146 * \param [in] VAL Value to rotate 147 * \param [in] SHIFT Number of Bits to rotate 148 * \return Rotated value 149 */ 150 #define __ROR(VAL, SHIFT) ((unsigned int)__ror(VAL, SHIFT)) 151 152 /** @} */ /* end of group CMSIS_Core_InstructionInterface */ 153 154 /* ################### Compiler specific Intrinsics ########################### */ 155 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics 156 * Access to dedicated SIMD instructions 157 * @{ 158 */ 159 #if (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) 160 161 #define __SADD8(VAL1, VAL2) ((unsigned int)_sadd8(VAL1, VAL2)) 162 #define __QADD8(VAL1, VAL2) ((unsigned int)_qadd8(VAL1, VAL2)) 163 #define __SHADD8(VAL1, VAL2) ((unsigned int)_shadd8(VAL1, VAL2)) 164 #define __UADD8(VAL1, VAL2) ((unsigned int)_uadd8(VAL1, VAL2)) 165 #define __UQADD8(VAL1, VAL2) ((unsigned int)_uqadd8(VAL1, VAL2)) 166 #define __UHADD8(VAL1, VAL2) ((unsigned int)_uhadd8(VAL1, VAL2)) 167 #define __SSUB8(VAL1, VAL2) ((unsigned int)_ssub8(VAL1, VAL2)) 168 #define __QSUB8(VAL1, VAL2) ((unsigned int)_qsub8(VAL1, VAL2)) 169 #define __SHSUB8(VAL1, VAL2) ((unsigned int)_shsub8(VAL1, VAL2)) 170 #define __USUB8(VAL1, VAL2) ((unsigned int)_usub8(VAL1, VAL2)) 171 #define __UQSUB8(VAL1, VAL2) ((unsigned int)_uqsub8(VAL1, VAL2)) 172 #define __UHSUB8(VAL1, VAL2) ((unsigned int)_uhsub8(VAL1, VAL2)) 173 #define __SADD16(VAL1, VAL2) ((unsigned int)_sadd16(VAL1, VAL2)) 174 #define __QADD16(VAL1, VAL2) ((unsigned int)_qadd16(VAL1, VAL2)) 175 #define __SHADD16(VAL1, VAL2) ((unsigned int)_shadd16(VAL1, VAL2)) 176 #define __UADD16(VAL1, VAL2) ((unsigned int)_uadd16(VAL1, VAL2)) 177 #define __UQADD16(VAL1, VAL2) ((unsigned int)_uqadd16(VAL1, VAL2)) 178 #define __UHADD16(VAL1, VAL2) ((unsigned int)_uhadd16(VAL1, VAL2)) 179 #define __SSUB16(VAL1, VAL2) ((unsigned int)_ssub16(VAL1, VAL2)) 180 #define __QSUB16(VAL1, VAL2) ((unsigned int)_qsub16(VAL1, VAL2)) 181 #define __SHSUB16(VAL1, VAL2) ((unsigned int)_shsub16(VAL1, VAL2)) 182 #define __USUB16(VAL1, VAL2) ((unsigned int)_usub16(VAL1, VAL2)) 183 #define __UQSUB16(VAL1, VAL2) ((unsigned int)_uqsub16(VAL1, VAL2)) 184 #define __UHSUB16(VAL1, VAL2) ((unsigned int)_uhsub16(VAL1, VAL2)) 185 #define __SASX(VAL1, VAL2) ((unsigned int)_saddsubx(VAL1, VAL2)) 186 #define __QASX(VAL1, VAL2) ((unsigned int)_qaddsubx(VAL1, VAL2)) 187 #define __SHASX(VAL1, VAL2) ((unsigned int)_shaddsubx(VAL1, VAL2)) 188 #define __UASX(VAL1, VAL2) ((unsigned int)_uaddsubx(VAL1, VAL2)) 189 #define __UQASX(VAL1, VAL2) ((unsigned int)_uqaddsubx(VAL1, VAL2)) 190 #define __UHASX(VAL1, VAL2) ((unsigned int)_uhaddsubx(VAL1, VAL2))) 191 #define __SSAX(VAL1, VAL2) ((unsigned int)_ssubaddx(VAL1, VAL2)) 192 #define __QSAX(VAL1, VAL2) ((unsigned int)_qsubaddx(VAL1, VAL2)) 193 #define __SHSAX(VAL1, VAL2) ((unsigned int)_shsubaddx(VAL1, VAL2)) 194 #define __USAX(VAL1, VAL2) ((unsigned int)_usubaddx(VAL1, VAL2)) 195 #define __UQSAX(VAL1, VAL2) ((unsigned int)_uqsubaddx(VAL1, VAL2)) 196 #define __UHSAX(VAL1, VAL2) ((unsigned int)_uhsubaddx(VAL1, VAL2)) 197 #define __USAD8(VAL1, VAL2) ((unsigned int)_usad8(VAL1, VAL2)) 198 #define __USADA8(VAL1, VAL2, VAL3) ((unsigned int)_usada8(VAL1, VAL2, VAL3)) 199 #define __SSAT16(VAL, BITPOS) ((unsigned int)_ssat16(VAL, BITPOS)) 200 #define __USAT16(VAL, BITPOS) ((unsigned int)_usat16(VAL, BITPOS)) 201 #define __UXTB16(VAL) ((unsigned int)_uxtb16(VAL, 0)) 202 #define __UXTAB16(VAL1, VAL2) ((unsigned int)_uxtab16(VAL1, VAL2, 0)) 203 #define __SXTB16(VAL) ((unsigned int)_sxtb16(VAL, 0)) 204 #define __SXTAB16(VAL1, VAL2) ((unsigned int)_sxtab16(VAL1, VAL2, 0)) 205 #define __SMUAD(VAL1, VAL2) ((unsigned int)_smuad(VAL1, VAL2)) 206 #define __SMUADX(VAL1, VAL2) ((unsigned int)_smuadx(VAL1, VAL2)) 207 #define __SMLAD(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smlad(VAL1, VAL2, ACCUMULATOR)) 208 #define __SMLADX(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smladx(VAL1, VAL2, ACCUMULATOR)) 209 #define __SMLALD(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlald(ACCUMULATOR, VAL1, VAL2)) 210 #define __SMLALDX(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlaldx(ACCUMULATOR, VAL1, VAL2)) 211 #define __SMUSD(VAL1, VAL2) ((unsigned int)_smusd(VAL1, VAL2)) 212 #define __SMUSDX(VAL1, VAL2) ((unsigned int)_smusdx(VAL1, VAL2)) 213 #define __SMLSD(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smlsd(VAL1, VAL2, ACCUMULATOR)) 214 #define __SMLSDX(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smlsdx(VAL1, VAL2, ACCUMULATOR)) 215 #define __SMLSLD(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlsld(ACCUMULATOR, VAL1, VAL2)) 216 #define __SMLSLDX(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlsldx(ACCUMULATOR, VAL1, VAL2)) 217 #define __SEL(VAL1, VAL2) ((unsigned int)_sel(VAL1, VAL2)) 218 #define __QADD _sadd 219 #define __QSUB _ssub 220 #define __PKHBT _pkhbt 221 #define __PKHTB _pkhtb 222 #define __SMMLA _smmla 223 224 #define __QDADD _sdadd 225 #define __QDSUB _sdsub 226 #define __SMLABB _smlabb 227 #define __SMLABT _smlabt 228 #define __SMLALBB _smlalbb 229 #define __SMLALBT _smlalbt 230 #define __SMLALTB _smlaltb 231 #define __SMLALTT _smlaltt 232 #define __SMLATB _smlatb 233 #define __SMLATT _smlatt 234 #define __SMLAWB _smlawb 235 #define __SMLAWT _smlawt 236 #define __SMULBB _smulbb 237 #define __SMULBT _smulbt 238 #define __SMULTB _smultb 239 #define __SMULTT _smultt 240 #define __SMULWB _smulwb 241 #define __SMULWT _smulwt 242 #define __SMMLAR _smmlar 243 #define __SMMLS _smmls 244 #define __SMMLSR _smmlsr 245 #define __SMMUL _smmul 246 #define __SMMULR _smmulr 247 #define __SXTAB _sxtab 248 #define __SXTAH _sxtah 249 #define __UMAAL _umaal 250 #define __UXTAB _uxtab 251 #define __UXTAH _uxtah 252 #define __SUBC _subc 253 254 #endif /* (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) */ 255 256 #if (defined (__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ == 1)) 257 258 #define __SXTB _sxtb 259 #define __SXTH _sxth 260 #define __UXTB _uxtb 261 #define __UXTH _uxth 262 263 #endif /* (defined (__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ == 1)) */ 264 265 /** @} */ /* end of group CMSIS_SIMD_intrinsics */ 266 267 #endif /* CMSIS_CCS_H_ */ 268