1 /**************************************************
2 *
3 * This file shall be included in appropriate CMSIS header
4 * files, to provide required functions and intrinsics when
5 * building with the IAR C/C++ Compiler for ARM (iccarm).
6 *
7 * Copyright 2011 IAR Systems. All rights reserved.
8 *
9 * $Revision: 50409 $
10 *
11 **************************************************/
12
13 #ifndef __CMSIS_IAR_H__
14 #define __CMSIS_IAR_H__
15
16 #ifndef __ICCARM__
17 #error This file should only be compiled by ICCARM
18 #endif
19
20 #pragma system_include
21
22 #include <intrinsics.h>
23
24 #if (__CORE__ == __ARM6M__)
25 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
26 #define __CLZ __cmsis_iar_clz
27 #define __SSAT __cmsis_iar_ssat
28 #endif
29
30 #pragma diag_suppress=Pe940
31 #pragma diag_suppress=Pe177
32
33 #define __enable_irq __enable_interrupt
34 #define __disable_irq __disable_interrupt
35 #define __NOP __no_operation
36
37 #if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
38
39 #if (__VER__ < 6010002) /* If iccarm version is older than 6.10.2 ---------- */
40
__get_APSR(void)41 static uint32_t __get_APSR(void)
42 {
43 __ASM("mrs r0, apsr");
44 }
45
__get_xPSR(void)46 static uint32_t __get_xPSR(void)
47 {
48 __ASM("mrs r0, psr"); /* assembler does not know "xpsr" */
49 }
50
51 #endif /* __VER__ < 6010002 */
52
__get_IPSR(void)53 static uint32_t __get_IPSR(void)
54 {
55 __ASM("mrs r0, ipsr");
56 }
57
__get_PSR(void)58 static uint32_t __get_PSR(void)
59 {
60 __ASM("mrs r0, psr");
61 }
62
__get_PSP(void)63 static uint32_t __get_PSP(void)
64 {
65 __ASM("mrs r0, psp");
66 }
67
__set_PSP(uint32_t topOfProcStack)68 static void __set_PSP(uint32_t topOfProcStack)
69 {
70 __ASM("msr psp, r0");
71 }
72
__get_MSP(void)73 static uint32_t __get_MSP(void)
74 {
75 __ASM("mrs r0, msp");
76 }
77
__set_MSP(uint32_t topOfMainStack)78 static void __set_MSP(uint32_t topOfMainStack)
79 {
80 __ASM("msr msp, r0");
81 }
82
__WFI(void)83 static __INLINE void __WFI(void)
84 {
85 __ASM ("wfi");
86 }
87
__WFE(void)88 static __INLINE void __WFE(void)
89 {
90 __ASM ("wfe");
91 }
92
__SEV(void)93 static __INLINE void __SEV(void)
94 {
95 __ASM ("sev");
96 }
97
__REV16(uint32_t value)98 static uint32_t __REV16(uint32_t value)
99 {
100 __ASM("rev16 r0, r0");
101 }
102
103 #else /* __VER__ < 6020000 */
104
__get_xPSR(void)105 static uint32_t __get_xPSR(void)
106 {
107 return __get_PSR(); /* __get_PSR() intrinsic introduced in iccarm 6.20 */
108 }
109
110 #endif /* __VER__ < 6020000 */
111
112 #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
113
114 #if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
115
__enable_fault_irq(void)116 static __INLINE void __enable_fault_irq(void)
117 {
118 __ASM ("cpsie f");
119 }
120
__disable_fault_irq(void)121 static __INLINE void __disable_fault_irq(void)
122 {
123 __ASM ("cpsid f");
124 }
125
__RBIT(uint32_t value)126 static uint32_t __RBIT(uint32_t value)
127 {
128 __ASM("rbit r0, r0");
129 }
130
__LDREXB(volatile uint8_t * addr)131 static uint8_t __LDREXB(volatile uint8_t *addr)
132 {
133 __ASM("ldrexb r0, [r0]");
134 }
135
__LDREXH(volatile uint16_t * addr)136 static uint16_t __LDREXH(volatile uint16_t *addr)
137 {
138 __ASM("ldrexh r0, [r0]");
139 }
140
__LDREXW(volatile uint32_t * addr)141 static uint32_t __LDREXW(volatile uint32_t *addr)
142 {
143 __ASM("ldrex r0, [r0]");
144 }
145
__STREXB(uint8_t value,volatile uint8_t * addr)146 static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
147 {
148 __ASM("strexb r0, r0, [r1]");
149 }
150
__STREXH(uint16_t value,volatile uint16_t * addr)151 static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
152 {
153 __ASM("strexh r0, r0, [r1]");
154 }
155
__STREXW(uint32_t value,volatile uint32_t * addr)156 static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
157 {
158 __ASM("strex r0, r0, [r1]");
159 }
160
__CLREX(void)161 static __INLINE void __CLREX(void)
162 {
163 __ASM ("clrex");
164 }
165
166 #else /* __VER__ >= 6020000 --------------------- */
167
168 #define __LDREXW __LDREX
169 #define __STREXW __STREX
170 #define __enable_fault_irq __enable_fiq
171 #define __disable_fault_irq __disable_fiq
172
173 #endif /* __VER__ < 6020000 */
174
175 #endif /* (__CORTEX_M >= 0x03) */
176
177 #if (__CORTEX_M == 0x04) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
178
179 #if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
180
__get_FPSCR(void)181 static uint32_t __get_FPSCR(void)
182 {
183 #if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */
184 __ASM("vmrs r0, fpscr");
185 #else
186 return(0);
187 #endif
188 }
189
__set_FPSCR(uint32_t fpscr)190 static void __set_FPSCR(uint32_t fpscr)
191 {
192 #if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */
193 __ASM("vmsr fpscr, r0");
194 #endif
195 }
196
197 #endif /* __VER__ < 6020000 */
198
199 #endif /* (__CORTEX_M == 0x04) */
200
__ROR(uint32_t op1,uint32_t op2)201 static __INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
202 {
203 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
204 }
205
206 #pragma diag_default=Pe940
207 #pragma diag_default=Pe177
208
209 #endif /* __CMSIS_IAR_H__ */
210