1 //###########################################################################
2 //
3 // FILE: F2837xD_EQep.c
4 //
5 // TITLE: F2837xD eQEP Initialization & Support Functions.
6 //
7 //###########################################################################
8 // $TI Release: F2837xD Support Library v3.05.00.00 $
9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
10 // $Copyright:
11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
12 //
13 // Redistribution and use in source and binary forms, with or without
14 // modification, are permitted provided that the following conditions
15 // are met:
16 //
17 // Redistributions of source code must retain the above copyright
18 // notice, this list of conditions and the following disclaimer.
19 //
20 // Redistributions in binary form must reproduce the above copyright
21 // notice, this list of conditions and the following disclaimer in the
22 // documentation and/or other materials provided with the
23 // distribution.
24 //
25 // Neither the name of Texas Instruments Incorporated nor the names of
26 // its contributors may be used to endorse or promote products derived
27 // from this software without specific prior written permission.
28 //
29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 // $
41 //###########################################################################
42
43 //
44 // Included Files
45 //
46 #include "F2837xD_device.h"
47 #include "F2837xD_Examples.h"
48
49 //
50 // InitEQep - This function initializes the eQEP(s) to a known state.
51 //
InitEQep(void)52 void InitEQep(void)
53 {
54 // Initialize eQEP1
55
56 //tbd...
57 }
58
59 //
60 // InitEQepGpio - This function initializes GPIO pins to function as eQEP pins
61 // Each GPIO pin can be configured as a GPIO pin or up to 3
62 // different peripheral functional pins. By default all pins
63 // come up as GPIO inputs after reset.
64 // Caution:
65 // For each eQEP peripheral
66 // Only one GPIO pin should be enabled for EQEPxA operation.
67 // Only one GPIO pin should be enabled for EQEPxB operation.
68 // Only one GPIO pin should be enabled for EQEPxS operation.
69 // Only one GPIO pin should be enabled for EQEPxI operation.
70 // Comment out other unwanted lines.
71 //
InitEQepGpio()72 void InitEQepGpio()
73 {
74 InitEQep1Gpio();
75 InitEQep2Gpio();
76 InitEQep3Gpio();
77 }
78
79 //
80 // InitEQep1Gpio - Initialize EQEP-1 GPIOs
81 // Caution:
82 // For each eQEP peripheral
83 // Only one GPIO pin should be enabled for EQEPxA operation.
84 // Only one GPIO pin should be enabled for EQEPxB operation.
85 // Only one GPIO pin should be enabled for EQEPxS operation.
86 // Only one GPIO pin should be enabled for EQEPxI operation.
87 // Comment out other unwanted lines.
88 //
InitEQep1Gpio(void)89 void InitEQep1Gpio(void)
90 {
91 EALLOW;
92
93 //
94 // Disable internal pull-up for the selected output pins
95 // for reduced power consumption
96 // Pull-ups can be enabled or disabled by the user.
97 // Comment out other unwanted lines.
98 //
99
100 // GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EQEP1A)
101 // GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EQEP1B)
102 // GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EQEP1S)
103 // GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EQEP1I)
104
105 GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (EQEP1A)
106 GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (EQEP1B)
107 GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; // Disable pull-up on GPIO22 (EQEP1S)
108 GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; // Disable pull-up on GPIO23 (EQEP1I)
109
110 // GpioCtrlRegs.GPBPUD.bit.GPIO50 = 1; // Disable pull-up on GPIO50 (EQEP1A)
111 // GpioCtrlRegs.GPBPUD.bit.GPIO51 = 1; // Disable pull-up on GPIO51 (EQEP1B)
112 // GpioCtrlRegs.GPBPUD.bit.GPIO52 = 1; // Disable pull-up on GPIO52 (EQEP1S)
113 // GpioCtrlRegs.GPBPUD.bit.GPIO53 = 1; // Disable pull-up on GPIO53 (EQEP1I)
114
115 // GpioCtrlRegs.GPDPUD.bit.GPIO96 = 1; // Disable pull-up on GPIO96 (EQEP1A)
116 // GpioCtrlRegs.GPDPUD.bit.GPIO97 = 1; // Disable pull-up on GPIO97 (EQEP1B)
117 // GpioCtrlRegs.GPDPUD.bit.GPIO98 = 1; // Disable pull-up on GPIO98 (EQEP1S)
118 // GpioCtrlRegs.GPDPUD.bit.GPIO99 = 1; // Disable pull-up on GPIO99 (EQEP1I)
119
120 //
121 // Synchronize inputs to SYSCLK
122 // Synchronization can be enabled or disabled by the user.
123 // Comment out other unwanted lines.
124 //
125
126 // GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 0; // Sync GPIO10 to SYSCLK (EQEP1A)
127 // GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Sync GPIO11 to SYSCLK (EQEP1B)
128 // GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Sync GPIO12 to SYSCLK (EQEP1S)
129 // GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Sync GPIO13 to SYSCLK (EQEP1I)
130
131 GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync GPIO20 to SYSCLK (EQEP1A)
132 GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync GPIO21 to SYSCLK (EQEP1B)
133 GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync GPIO22 to SYSCLK (EQEP1S)
134 GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync GPIO23 to SYSCLK (EQEP1I)
135
136 // GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync GPIO50 to SYSCLK (EQEP1A)
137 // GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync GPIO51 to SYSCLK (EQEP1B)
138 // GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync GPIO52 to SYSCLK (EQEP1S)
139 // GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync GPIO53 to SYSCLK (EQEP1I)
140
141 // GpioCtrlRegs.GPDQSEL1.bit.GPIO96 = 0; // Sync GPIO96 to SYSCLK (EQEP1A)
142 // GpioCtrlRegs.GPDQSEL1.bit.GPIO97 = 0; // Sync GPIO97 to SYSCLK (EQEP1B)
143 // GpioCtrlRegs.GPDQSEL1.bit.GPIO98 = 0; // Sync GPIO98 to SYSCLK (EQEP1S)
144 // GpioCtrlRegs.GPDQSEL1.bit.GPIO99 = 0; // Sync GPIO99 to SYSCLK (EQEP1I)
145
146 //
147 // Configure EQEP-1 pins using GPIO regs
148 // This specifies which of the possible GPIO pins will be EQEP1 functional
149 // pins.
150 // Comment out other unwanted lines.
151 //
152
153 // GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A
154 // GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A
155 // GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B
156 // GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B
157 // GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S
158 // GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S
159 // GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I
160 // GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I
161
162 GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A
163 GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B
164 GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S
165 GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I
166
167 // GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A
168 // GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B
169 // GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S
170 // GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I
171
172 // GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A
173 // GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A
174 // GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B
175 // GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B
176 // GpioCtrlRegs.GPDGMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S
177 // GpioCtrlRegs.GPDMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S
178 // GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I
179 // GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I
180
181 EDIS;
182 }
183
184 //
185 // InitEQep2Gpio - Initialize EQEP-2 GPIOs
186 //
InitEQep2Gpio(void)187 void InitEQep2Gpio(void)
188 {
189 EALLOW;
190
191 //
192 // Disable internal pull-up for the selected output pins
193 // for reduced power consumption
194 // Pull-ups can be enabled or disabled by the user.
195 // Comment out other unwanted lines.
196 //
197 GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // Disable pull-up on GPIO24 (EQEP2A)
198 GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; // Disable pull-up on GPIO25 (EQEP2B)
199 GpioCtrlRegs.GPAPUD.bit.GPIO26 = 1; // Disable pull-up on GPIO26 (EQEP2S)
200 GpioCtrlRegs.GPAPUD.bit.GPIO27 = 1; // Disable pull-up on GPIO27 (EQEP2I)
201
202 // GpioCtrlRegs.GPBPUD.bit.GPIO54 = 1; // Disable pull-up on GPIO54 (EQEP2A)
203 // GpioCtrlRegs.GPBPUD.bit.GPIO55 = 1; // Disable pull-up on GPIO55 (EQEP2B)
204 // GpioCtrlRegs.GPBPUD.bit.GPIO56 = 1; // Disable pull-up on GPIO56 (EQEP2S)
205 // GpioCtrlRegs.GPBPUD.bit.GPIO57 = 1; // Disable pull-up on GPIO57 (EQEP2I)
206
207 // GpioCtrlRegs.GPCPUD.bit.GPIO78 = 1; // Disable pull-up on GPIO78 (EQEP2A)
208 // GpioCtrlRegs.GPCPUD.bit.GPIO79 = 1; // Disable pull-up on GPIO79 (EQEP2B)
209 // GpioCtrlRegs.GPCPUD.bit.GPIO80 = 1; // Disable pull-up on GPIO80 (EQEP2S)
210 // GpioCtrlRegs.GPCPUD.bit.GPIO81 = 1; // Disable pull-up on GPIO81 (EQEP2I)
211
212 // GpioCtrlRegs.GPDPUD.bit.GPIO100 = 1; // Disable pull-up on GPIO100 (EQEP2A)
213 // GpioCtrlRegs.GPDPUD.bit.GPIO101 = 1; // Disable pull-up on GPIO101 (EQEP2B)
214 // GpioCtrlRegs.GPDPUD.bit.GPIO102 = 1; // Disable pull-up on GPIO102 (EQEP2S)
215 // GpioCtrlRegs.GPDPUD.bit.GPIO103 = 1; // Disable pull-up on GPIO103 (EQEP2I)
216
217 //
218 // Synchronize inputs to SYSCLK
219 // Synchronization can be enabled or disabled by the user.
220 // Comment out other unwanted lines.
221 //
222 GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync GPIO24 to SYSCLK (EQEP2A)
223 GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync GPIO25 to SYSCLK (EQEP2B)
224 GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync GPIO26 to SYSCLK (EQEP2S)
225 GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync GPIO27 to SYSCLK (EQEP2I)
226
227 // GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; // Sync GPIO54 to SYSCLK (EQEP2A)
228 // GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 0; // Sync GPIO55 to SYSCLK (EQEP2B)
229 // GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 0; // Sync GPIO56 to SYSCLK (EQEP2S)
230 // GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 0; // Sync GPIO57 to SYSCLK (EQEP2I)
231
232 // GpioCtrlRegs.GPCQSEL1.bit.GPIO78 = 0; // Sync GPIO78 to SYSCLK (EQEP2A)
233 // GpioCtrlRegs.GPCQSEL1.bit.GPIO79 = 0; // Sync GPIO79 to SYSCLK (EQEP2B)
234 // GpioCtrlRegs.GPCQSEL2.bit.GPIO80 = 0; // Sync GPIO80 to SYSCLK (EQEP2S)
235 // GpioCtrlRegs.GPCQSEL2.bit.GPIO81 = 0; // Sync GPIO81 to SYSCLK (EQEP2I)
236
237 // GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 0; // Sync GPIO100 to SYSCLK (EQEP2A)
238 // GpioCtrlRegs.GPDQSEL1.bit.GPIO101 = 0; // Sync GPIO101 to SYSCLK (EQEP2B)
239 // GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 0; // Sync GPIO102 to SYSCLK (EQEP2S)
240 // GpioCtrlRegs.GPDQSEL1.bit.GPIO103 = 0; // Sync GPIO103 to SYSCLK (EQEP2I)
241
242 //
243 // Configure EQEP-1 pins using GPIO regs
244 // This specifies which of the possible GPIO pins will be EQEP2 functional pins.
245 // Comment out other unwanted lines.
246 //
247 GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A
248 GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B
249 GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2S
250 GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2I
251
252 // GpioCtrlRegs.GPBGMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A
253 // GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A
254 // GpioCtrlRegs.GPBGMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B
255 // GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B
256 // GpioCtrlRegs.GPBGMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S
257 // GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S
258 // GpioCtrlRegs.GPBGMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I
259 // GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I
260
261 // GpioCtrlRegs.GPCGMUX1.bit.GPIO78 = 1; // Configure GPIO78 as EQEP2A
262 // GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 2; // Configure GPIO78 as EQEP2A
263 // GpioCtrlRegs.GPCGMUX1.bit.GPIO79 = 1; // Configure GPIO79 as EQEP2B
264 // GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 2; // Configure GPIO79 as EQEP2B
265 // GpioCtrlRegs.GPCGMUX2.bit.GPIO80 = 1; // Configure GPIO80 as EQEP2S
266 // GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 2; // Configure GPIO80 as EQEP2S
267 // GpioCtrlRegs.GPCGMUX2.bit.GPIO81 = 1; // Configure GPIO81 as EQEP2I
268 // GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 2; // Configure GPIO81 as EQEP2I
269
270 // GpioCtrlRegs.GPDGMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A
271 // GpioCtrlRegs.GPDMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A
272 // GpioCtrlRegs.GPDGMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B
273 // GpioCtrlRegs.GPDMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B
274 // GpioCtrlRegs.GPDGMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S
275 // GpioCtrlRegs.GPDMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S
276 // GpioCtrlRegs.GPDGMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I
277 // GpioCtrlRegs.GPDMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I
278
279 EDIS;
280 }
281
282 //
283 // InitEQep3Gpio - Initialize EQEP-3 GPIOs
284 //
InitEQep3Gpio(void)285 void InitEQep3Gpio(void)
286 {
287 EALLOW;
288
289 //
290 // Disable internal pull-up for the selected output pins
291 // for reduced power consumption
292 // Pull-ups can be enabled or disabled by the user.
293 // Comment out other unwanted lines.
294 //
295
296 // GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EQEP3A)
297 // GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EQEP3B)
298 // GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EQEP3S)
299 // GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EQEP3I)
300
301 GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up on GPIO28 (EQEP3A)
302 GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1; // Disable pull-up on GPIO29 (EQEP3B)
303 GpioCtrlRegs.GPAPUD.bit.GPIO30 = 1; // Disable pull-up on GPIO30 (EQEP3S)
304 GpioCtrlRegs.GPAPUD.bit.GPIO31 = 1; // Disable pull-up on GPIO31 (EQEP3I)
305
306 // GpioCtrlRegs.GPBPUD.bit.GPIO62 = 1; // Disable pull-up on GPIO62 (EQEP3A)
307 // GpioCtrlRegs.GPBPUD.bit.GPIO63 = 1; // Disable pull-up on GPIO63 (EQEP3B)
308 // GpioCtrlRegs.GPCPUD.bit.GPIO64 = 1; // Disable pull-up on GPIO64 (EQEP3S)
309 // GpioCtrlRegs.GPCPUD.bit.GPIO65 = 1; // Disable pull-up on GPIO65 (EQEP3I)
310
311 // GpioCtrlRegs.GPDPUD.bit.GPIO104 = 1; // Disable pull-up on GPIO104 (EQEP3A)
312 // GpioCtrlRegs.GPDPUD.bit.GPIO105 = 1; // Disable pull-up on GPIO105 (EQEP3B)
313 // GpioCtrlRegs.GPDPUD.bit.GPIO106 = 1; // Disable pull-up on GPIO106 (EQEP3S)
314 // GpioCtrlRegs.GPDPUD.bit.GPIO107 = 1; // Disable pull-up on GPIO107 (EQEP3I)
315
316 //
317 // Synchronize inputs to SYSCLK
318 // Synchronization can be enabled or disabled by the user.
319 // Comment out other unwanted lines.
320 //
321
322 // GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Sync GPIO6 to SYSCLK (EQEP3A)
323 // GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Sync GPIO7 to SYSCLK (EQEP3B)
324 // GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0; // Sync GPIO8 to SYSCLK (EQEP3S)
325 // GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Sync GPIO9 to SYSCLK (EQEP3I)
326
327 GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 0; // Sync GPIO28 to SYSCLK (EQEP3A)
328 GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 0; // Sync GPIO29 to SYSCLK (EQEP3B)
329 GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 0; // Sync GPIO30 to SYSCLK (EQEP3S)
330 GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 0; // Sync GPIO31 to SYSCLK (EQEP3I)
331
332 // GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 0; // Sync GPIO62 to SYSCLK (EQEP3A)
333 // GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0; // Sync GPIO63 to SYSCLK (EQEP3B)
334 // GpioCtrlRegs.GPCQSEL1.bit.GPIO64 = 0; // Sync GPIO64 to SYSCLK (EQEP3S)
335 // GpioCtrlRegs.GPCQSEL1.bit.GPIO65 = 0; // Sync GPIO65 to SYSCLK (EQEP3I)
336
337 // GpioCtrlRegs.GPDQSEL1.bit.GPIO104 = 0; // Sync GPIO104 to SYSCLK (EQEP3A)
338 // GpioCtrlRegs.GPDQSEL1.bit.GPIO105 = 0; // Sync GPIO105 to SYSCLK (EQEP3B)
339 // GpioCtrlRegs.GPDQSEL1.bit.GPIO106 = 0; // Sync GPIO106 to SYSCLK (EQEP3S)
340 // GpioCtrlRegs.GPDQSEL1.bit.GPIO107 = 0; // Sync GPIO107 to SYSCLK (EQEP3I)
341
342 //
343 // Configure EQEP-1 pins using GPIO regs
344 // This specifies which of the possible GPIO pins will be EQEP3 functional pins.
345 // Comment out other unwanted lines.
346 //
347
348 // GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A
349 // GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A
350 // GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B
351 // GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B
352 // GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S
353 // GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S
354 // GpioCtrlRegs.GPAGMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I
355 // GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I
356
357 GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 1; // Configure GPIO28 as EQEP3A
358 GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 2; // Configure GPIO28 as EQEP3A
359 GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 1; // Configure GPIO29 as EQEP3B
360 GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 2; // Configure GPIO29 as EQEP3B
361 GpioCtrlRegs.GPAGMUX2.bit.GPIO30 = 1; // Configure GPIO30 as EQEP3S
362 GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 2; // Configure GPIO30 as EQEP3S
363 GpioCtrlRegs.GPAGMUX2.bit.GPIO31 = 1; // Configure GPIO31 as EQEP3I
364 GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 2; // Configure GPIO31 as EQEP3I
365
366 // GpioCtrlRegs.GPBGMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A
367 // GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A
368 // GpioCtrlRegs.GPBGMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B
369 // GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B
370 // GpioCtrlRegs.GPCGMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S
371 // GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S
372 // GpioCtrlRegs.GPCGMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I
373 // GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I
374
375 // GpioCtrlRegs.GPDGMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A
376 // GpioCtrlRegs.GPDMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A
377 // GpioCtrlRegs.GPDGMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B
378 // GpioCtrlRegs.GPDMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B
379 // GpioCtrlRegs.GPDGMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S
380 // GpioCtrlRegs.GPDMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S
381 // GpioCtrlRegs.GPDGMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I
382 // GpioCtrlRegs.GPDMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I
383
384 EDIS;
385 }
386
387 //
388 // End of file
389 //
390