1 //###########################################################################
2 //
3 // FILE: F2837xD_PieVect.c
4 //
5 // TITLE: F2837xD Device PIE Vector Initialization Functions
6 //
7 //###########################################################################
8 // $TI Release: F2837xD Support Library v3.05.00.00 $
9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
10 // $Copyright:
11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
12 //
13 // Redistribution and use in source and binary forms, with or without
14 // modification, are permitted provided that the following conditions
15 // are met:
16 //
17 // Redistributions of source code must retain the above copyright
18 // notice, this list of conditions and the following disclaimer.
19 //
20 // Redistributions in binary form must reproduce the above copyright
21 // notice, this list of conditions and the following disclaimer in the
22 // documentation and/or other materials provided with the
23 // distribution.
24 //
25 // Neither the name of Texas Instruments Incorporated nor the names of
26 // its contributors may be used to endorse or promote products derived
27 // from this software without specific prior written permission.
28 //
29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 // $
41 //###########################################################################
42
43 //
44 // Included Files
45 //
46 #include "F2837xD_device.h"
47 #include "F2837xD_Examples.h"
48
49 //
50 // Globals
51 //
52 const struct PIE_VECT_TABLE PieVectTableInit = {
53 PIE_RESERVED_ISR, // Reserved
54 PIE_RESERVED_ISR, // Reserved
55 PIE_RESERVED_ISR, // Reserved
56 PIE_RESERVED_ISR, // Reserved
57 PIE_RESERVED_ISR, // Reserved
58 PIE_RESERVED_ISR, // Reserved
59 PIE_RESERVED_ISR, // Reserved
60 PIE_RESERVED_ISR, // Reserved
61 PIE_RESERVED_ISR, // Reserved
62 PIE_RESERVED_ISR, // Reserved
63 PIE_RESERVED_ISR, // Reserved
64 PIE_RESERVED_ISR, // Reserved
65 PIE_RESERVED_ISR, // Reserved
66 TIMER1_ISR, // CPU Timer 1 Interrupt
67 TIMER2_ISR, // CPU Timer 2 Interrupt
68 DATALOG_ISR, // Datalogging Interrupt
69 RTOS_ISR, // RTOS Interrupt
70 EMU_ISR, // Emulation Interrupt
71 NMI_ISR, // Non-Maskable Interrupt
72 ILLEGAL_ISR, // Illegal Operation Trap
73 USER1_ISR, // User Defined Trap 1
74 USER2_ISR, // User Defined Trap 2
75 USER3_ISR, // User Defined Trap 3
76 USER4_ISR, // User Defined Trap 4
77 USER5_ISR, // User Defined Trap 5
78 USER6_ISR, // User Defined Trap 6
79 USER7_ISR, // User Defined Trap 7
80 USER8_ISR, // User Defined Trap 8
81 USER9_ISR, // User Defined Trap 9
82 USER10_ISR, // User Defined Trap 10
83 USER11_ISR, // User Defined Trap 11
84 USER12_ISR, // User Defined Trap 12
85 ADCA1_ISR, // 1.1 - ADCA Interrupt 1
86 ADCB1_ISR, // 1.2 - ADCB Interrupt 1
87 ADCC1_ISR, // 1.3 - ADCC Interrupt 1
88 XINT1_ISR, // 1.4 - XINT1 Interrupt
89 XINT2_ISR, // 1.5 - XINT2 Interrupt
90 ADCD1_ISR, // 1.6 - ADCD Interrupt 1
91 TIMER0_ISR, // 1.7 - Timer 0 Interrupt
92 WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt
93 EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt
94 EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt
95 EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt
96 EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt
97 EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt
98 EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt
99 EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt
100 EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt
101 EPWM1_ISR, // 3.1 - ePWM1 Interrupt
102 EPWM2_ISR, // 3.2 - ePWM2 Interrupt
103 EPWM3_ISR, // 3.3 - ePWM3 Interrupt
104 EPWM4_ISR, // 3.4 - ePWM4 Interrupt
105 EPWM5_ISR, // 3.5 - ePWM5 Interrupt
106 EPWM6_ISR, // 3.6 - ePWM6 Interrupt
107 EPWM7_ISR, // 3.7 - ePWM7 Interrupt
108 EPWM8_ISR, // 3.8 - ePWM8 Interrupt
109 ECAP1_ISR, // 4.1 - eCAP1 Interrupt
110 ECAP2_ISR, // 4.2 - eCAP2 Interrupt
111 ECAP3_ISR, // 4.3 - eCAP3 Interrupt
112 ECAP4_ISR, // 4.4 - eCAP4 Interrupt
113 ECAP5_ISR, // 4.5 - eCAP5 Interrupt
114 ECAP6_ISR, // 4.6 - eCAP6 Interrupt
115 PIE_RESERVED_ISR, // 4.7 - Reserved
116 PIE_RESERVED_ISR, // 4.8 - Reserved
117 EQEP1_ISR, // 5.1 - eQEP1 Interrupt
118 EQEP2_ISR, // 5.2 - eQEP2 Interrupt
119 EQEP3_ISR, // 5.3 - eQEP3 Interrupt
120 PIE_RESERVED_ISR, // 5.4 - Reserved
121 PIE_RESERVED_ISR, // 5.5 - Reserved
122 PIE_RESERVED_ISR, // 5.6 - Reserved
123 PIE_RESERVED_ISR, // 5.7 - Reserved
124 PIE_RESERVED_ISR, // 5.8 - Reserved
125 SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt
126 SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt
127 SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt
128 SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt
129 MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt
130 MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt
131 MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt
132 MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt
133 DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt
134 DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt
135 DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt
136 DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt
137 DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt
138 DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt
139 PIE_RESERVED_ISR, // 7.7 - Reserved
140 PIE_RESERVED_ISR, // 7.8 - Reserved
141 I2CA_ISR, // 8.1 - I2CA Interrupt 1
142 I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2
143 I2CB_ISR, // 8.3 - I2CB Interrupt 1
144 I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2
145 SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt
146 SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt
147 SCID_RX_ISR, // 8.7 - SCID Receive Interrupt
148 SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt
149 SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt
150 SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt
151 SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt
152 SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt
153 CANA0_ISR, // 9.5 - CANA Interrupt 0
154 CANA1_ISR, // 9.6 - CANA Interrupt 1
155 CANB0_ISR, // 9.7 - CANB Interrupt 0
156 CANB1_ISR, // 9.8 - CANB Interrupt 1
157 ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt
158 ADCA2_ISR, // 10.2 - ADCA Interrupt 2
159 ADCA3_ISR, // 10.3 - ADCA Interrupt 3
160 ADCA4_ISR, // 10.4 - ADCA Interrupt 4
161 ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt
162 ADCB2_ISR, // 10.6 - ADCB Interrupt 2
163 ADCB3_ISR, // 10.7 - ADCB Interrupt 3
164 ADCB4_ISR, // 10.8 - ADCB Interrupt 4
165 CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1
166 CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2
167 CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3
168 CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4
169 CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5
170 CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6
171 CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7
172 CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8
173 XINT3_ISR, // 12.1 - XINT3 Interrupt
174 XINT4_ISR, // 12.2 - XINT4 Interrupt
175 XINT5_ISR, // 12.3 - XINT5 Interrupt
176 PIE_RESERVED_ISR, // 12.4 - Reserved
177 PIE_RESERVED_ISR, // 12.5 - Reserved
178 VCU_ISR, // 12.6 - VCU Interrupt
179 FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt
180 FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt
181 PIE_RESERVED_ISR, // 1.9 - Reserved
182 PIE_RESERVED_ISR, // 1.10 - Reserved
183 PIE_RESERVED_ISR, // 1.11 - Reserved
184 PIE_RESERVED_ISR, // 1.12 - Reserved
185 IPC0_ISR, // 1.13 - IPC Interrupt 0
186 IPC1_ISR, // 1.14 - IPC Interrupt 1
187 IPC2_ISR, // 1.15 - IPC Interrupt 2
188 IPC3_ISR, // 1.16 - IPC Interrupt 3
189 EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt
190 EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt
191 EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt
192 EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt
193 PIE_RESERVED_ISR, // 2.13 - Reserved
194 PIE_RESERVED_ISR, // 2.14 - Reserved
195 PIE_RESERVED_ISR, // 2.15 - Reserved
196 PIE_RESERVED_ISR, // 2.16 - Reserved
197 EPWM9_ISR, // 3.9 - ePWM9 Interrupt
198 EPWM10_ISR, // 3.10 - ePWM10 Interrupt
199 EPWM11_ISR, // 3.11 - ePWM11 Interrupt
200 EPWM12_ISR, // 3.12 - ePWM12 Interrupt
201 PIE_RESERVED_ISR, // 3.13 - Reserved
202 PIE_RESERVED_ISR, // 3.14 - Reserved
203 PIE_RESERVED_ISR, // 3.15 - Reserved
204 PIE_RESERVED_ISR, // 3.16 - Reserved
205 PIE_RESERVED_ISR, // 4.9 - Reserved
206 PIE_RESERVED_ISR, // 4.10 - Reserved
207 PIE_RESERVED_ISR, // 4.11 - Reserved
208 PIE_RESERVED_ISR, // 4.12 - Reserved
209 PIE_RESERVED_ISR, // 4.13 - Reserved
210 PIE_RESERVED_ISR, // 4.14 - Reserved
211 PIE_RESERVED_ISR, // 4.15 - Reserved
212 PIE_RESERVED_ISR, // 4.16 - Reserved
213 SD1_ISR, // 5.9 - SD1 Interrupt
214 SD2_ISR, // 5.10 - SD2 Interrupt
215 PIE_RESERVED_ISR, // 5.11 - Reserved
216 PIE_RESERVED_ISR, // 5.12 - Reserved
217 PIE_RESERVED_ISR, // 5.13 - Reserved
218 PIE_RESERVED_ISR, // 5.14 - Reserved
219 PIE_RESERVED_ISR, // 5.15 - Reserved
220 PIE_RESERVED_ISR, // 5.16 - Reserved
221 SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt
222 SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt
223 PIE_RESERVED_ISR, // 6.11 - Reserved
224 PIE_RESERVED_ISR, // 6.12 - Reserved
225 PIE_RESERVED_ISR, // 6.13 - Reserved
226 PIE_RESERVED_ISR, // 6.14 - Reserved
227 PIE_RESERVED_ISR, // 6.15 - Reserved
228 PIE_RESERVED_ISR, // 6.16 - Reserved
229 PIE_RESERVED_ISR, // 7.9 - Reserved
230 PIE_RESERVED_ISR, // 7.10 - Reserved
231 PIE_RESERVED_ISR, // 7.11 - Reserved
232 PIE_RESERVED_ISR, // 7.12 - Reserved
233 PIE_RESERVED_ISR, // 7.13 - Reserved
234 PIE_RESERVED_ISR, // 7.14 - Reserved
235 PIE_RESERVED_ISR, // 7.15 - Reserved
236 PIE_RESERVED_ISR, // 7.16 - Reserved
237 PIE_RESERVED_ISR, // 8.9 - Reserved
238 PIE_RESERVED_ISR, // 8.10 - Reserved
239 PIE_RESERVED_ISR, // 8.11 - Reserved
240 PIE_RESERVED_ISR, // 8.12 - Reserved
241 PIE_RESERVED_ISR, // 8.13 - Reserved
242 PIE_RESERVED_ISR, // 8.14 - Reserved
243 #ifdef CPU1
244 UPPA_ISR, // 8.15 - uPPA Interrupt
245 PIE_RESERVED_ISR, // 8.16 - Reserved
246 #elif defined(CPU2)
247 PIE_RESERVED_ISR, // 8.15 - Reserved
248 PIE_RESERVED_ISR, // 8.16 - Reserved
249 #endif
250 PIE_RESERVED_ISR, // 9.9 - Reserved
251 PIE_RESERVED_ISR, // 9.10 - Reserved
252 PIE_RESERVED_ISR, // 9.11 - Reserved
253 PIE_RESERVED_ISR, // 9.12 - Reserved
254 PIE_RESERVED_ISR, // 9.13 - Reserved
255 PIE_RESERVED_ISR, // 9.14 - Reserved
256 #ifdef CPU1
257 USBA_ISR, // 9.15 - USBA Interrupt
258 #elif defined(CPU2)
259 PIE_RESERVED_ISR, // 9.15 - Reserved
260 #endif
261 PIE_RESERVED_ISR, // 9.16 - Reserved
262 ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt
263 ADCC2_ISR, // 10.10 - ADCC Interrupt 2
264 ADCC3_ISR, // 10.11 - ADCC Interrupt 3
265 ADCC4_ISR, // 10.12 - ADCC Interrupt 4
266 ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt
267 ADCD2_ISR, // 10.14 - ADCD Interrupt 2
268 ADCD3_ISR, // 10.15 - ADCD Interrupt 3
269 ADCD4_ISR, // 10.16 - ADCD Interrupt 4
270 PIE_RESERVED_ISR, // 11.9 - Reserved
271 PIE_RESERVED_ISR, // 11.10 - Reserved
272 PIE_RESERVED_ISR, // 11.11 - Reserved
273 PIE_RESERVED_ISR, // 11.12 - Reserved
274 PIE_RESERVED_ISR, // 11.13 - Reserved
275 PIE_RESERVED_ISR, // 11.14 - Reserved
276 PIE_RESERVED_ISR, // 11.15 - Reserved
277 PIE_RESERVED_ISR, // 11.16 - Reserved
278 EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt
279 RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt
280 FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt
281 RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt
282 SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt
283 AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt
284 CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt
285 CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt
286 };
287
288 //
289 // InitPieVectTable - This function initializes the PIE vector table to a
290 // known state and must be executed after boot time.
291 //
InitPieVectTable(void)292 void InitPieVectTable(void)
293 {
294 Uint16 i;
295 Uint32 *Source = (void *) &PieVectTableInit;
296 Uint32 *Dest = (void *) &PieVectTable;
297
298 //
299 // Do not write over first 3 32-bit locations (these locations are
300 // initialized by Boot ROM with boot variables)
301 //
302 Source = Source + 3;
303 Dest = Dest + 3;
304
305 EALLOW;
306 for(i = 0; i < 221; i++)
307 {
308 *Dest++ = *Source++;
309 }
310 EDIS;
311
312 //
313 // Enable the PIE Vector Table
314 //
315 PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
316 }
317
318 //
319 // End of file
320 //
321