1 /* 2 * =========================================================================================== 3 * 4 * Filename: common_cir.h 5 * 6 * Description: IR HAL definition. 7 * 8 * Version: Melis3.0 9 * Create: 2021-01-15 11:11:56 10 * Revision: none 11 * Compiler: GCC:version 9.2.1 12 * 13 * Author: luruixiang@allwinnertech.com 14 * Organization: SWC-BPD 15 * Last Modified: 2021-01-15 16:02:11 16 * 17 * =========================================================================================== 18 */ 19 20 #ifndef _CIRCOMMON_H_ 21 #define _CIRCOMMON_H_ 22 23 #ifdef __cplusplus 24 extern "C" 25 { 26 #endif 27 28 /* Registers */ 29 #define CIR_CTRL (0x00) /* IR Control */ 30 #define CIR_RXCTRL (0x10) /* Rx Config */ 31 #define CIR_RXFIFO (0x20) /* Rx Data */ 32 #define CIR_RXINT (0x2C) /* Rx Interrupt Enable */ 33 #define CIR_RXSTA (0x30) /* Rx Interrupt Status */ 34 #define CIR_CONFIG (0x34) /* IR Sample Config */ 35 36 /*CIR_CTRL*/ 37 #define GEN_OFFSET 0 38 #define RXEN_OFFSET 1 39 #define CIR_ENABLE_OFFSET 4 40 #define CIR_MODE_OFFSET 6 41 /*global enable*/ 42 #define GEN (0x01 << GEN_OFFSET) 43 /*receiver block enable*/ 44 #define RXEN (0x01 << RXEN_OFFSET) 45 /*cir enable*/ 46 #define CIR_ENABLE (0x03 << CIR_ENABLE_OFFSET) 47 /*active pulse accept mode*/ 48 #define CIR_MODE (0x03 << CIR_MODE_OFFSET) 49 50 /*CIR_RXCTRL*/ 51 #define RPPI_OFFSET 2 52 #define RPPI (0x01 << RPPI_OFFSET) /*receiver pulse polarity invert*/ 53 54 /*CIR_RXINT*/ 55 #define ROI_EN_OFFSET 0 56 #define PREI_EN_OFFSET 1 57 #define RAI_EN_OFFSET 4 58 #define DRQ_EN_OFFSET 5 59 #define RAL_OFFSET 8 60 /*receiver fifo overrun interrupt enable*/ 61 #define ROI_EN (0x01 << ROI_EN_OFFSET) 62 /*receiver packet end interrupt enable*/ 63 #define PREI_EN (0x01 << PREI_EN_OFFSET) 64 /*rx fifo available interrupt enable*/ 65 #define RAI_EN (0x01 << RAI_EN_OFFSET) 66 /*rx fifo dma enable*/ 67 #define DRQ_EN (0x01 << DRQ_EN_OFFSET) 68 /*rx fifo available received byte level*/ 69 #define RAL (0x3f << RAL_OFFSET) 70 #define IRQ_MASK (0x3f) 71 72 /*CIR_RXSTA*/ 73 #define ROI_OFFSET 0 74 #define RPE_OFFSET 1 75 #define RA_OFFSET 4 76 #define STAT_OFFSET 7 77 #define RAC_OFFSET 8 78 #define ROI (0x01 << ROI_OFFSET) /*receiver fifo overrun*/ 79 #define RPE (0x01 << RPE_OFFSET) /*receiver packet end reg*/ 80 #define RA (0x01 << RA_OFFSET) /*rx fifo available*/ 81 #define STAT (0x01 << STAT_OFFSET) /*status of cir, 0:idle, 1:busy*/ 82 #define RAC (0x7f << RAC_OFFSET) /*rx fifo available counter*/ 83 84 /*CIR_CONFIG*/ 85 #define SCS_OFFSET 0 86 #define NTHR_OFFSET 2 87 #define ITHR_OFFSET 8 88 #define ATHR_OFFSET 16 89 #define ATHC_OFFSET 23 90 #define SCS2_OFFSET 24 91 #define SCS (0x03 << SCS_OFFSET) /*sample clk select for cir*/ 92 #define NTHR (0x3f << NTHR_OFFSET) /*noise threshold for cir*/ 93 #define ITHR (0xff << ITHR_OFFSET) /*idle threshold for cir*/ 94 #define ATHR (0x7f << ATHR_OFFSET) /*active threshold for cir*/ 95 #define ATHC (0x01 << ATHC_OFFSET) /*active threshold control for cir*/ 96 #define SCS2 (0x01 << SCS2_OFFSET) /*bit2 of sample clock select for cir*/ 97 98 #define CIR_NOISE_THR_NEC 32 99 #define CIR_NOISE_THR_RC5 22 100 101 #ifdef __cplusplus 102 } 103 #endif 104 105 #endif 106