1 /** 2 * \file 3 * 4 * \brief SAM SLCD Driver Configuration Header 5 * 6 * Copyright (C) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 #ifndef CONF_SLCD_H_INCLUDED 47 #define CONF_SLCD_H_INCLUDED 48 49 /** Select SLCD clock. Use 32.768KHz OSCULP32K or XOSC32K for SLCD clock. 50 * 0 : From OSCULP32K 51 * 1 : From XOSC32K 52 */ 53 #define CONF_SLCD_CLOCK_SOURCE 0 54 55 /** SLCD Duty Setting 56 * 0:Static duty 57 * 1:1/2 duty 58 * 2:1/3 duty 59 * 3:1/4 duty 60 * 4:1/6 duty 61 * 5:1/8 duty 62 */ 63 #define CONF_SLCD_DUTY 5 64 65 /** 66 * SLCD Bias Setting. 67 * 0:Static bias 68 * 1:1/2 bias 69 * 2:1/3 bias 70 * 3:1/4 bias 71 */ 72 #define CONF_SLCD_BIAS 3 73 74 /** 75 * SLCD Frame Frequency. 76 * The optimal frame frequency should be in range from 30Hz up to 100Hz 77 * to avoid flickering and ghosting effect. 78 * To get the frame frequency, CLK_SLCD_OSC is first divided by a prescaler 79 * from 16 to 128 then divided by 1 up to 8 as following. 80 * 81 * FrameRate = CLK_SLCD_OSC / (PVAL*(CKDIV+1)*(DUTY+1)) 82 * 83 * SLCD Prescaler Value (PVAL). 84 * 0 : 16 prescaler 85 * 1 : 32 prescaler 86 * 2 : 64 prescaler 87 * 3 : 128 prescaler 88 * 89 * SLCD Clock divider (CKDIV) 90 * 0 : CKDIV is 0,divided by 1 91 * 1 : CKDIV is 1,divided by 2 92 * 2 : CKDIV is 2,divided by 3 93 * 3 : CKDIV is 3,divided by 4 94 * 4 : CKDIV is 4,divided by 5 95 * 5 : CKDIV is 5,divided by 6 96 * 6 : CKDIV is 6,divided by 7 97 * 7 : CKDIV is 7,divided by 8 98 */ 99 /** 100 * With 1/8 DUTY and the following configuration(16 prescaler and CKDIV value is 7), 101 * FrameRate = 32768/(16*(7+1)*8) = 32Hz 102 */ 103 #define CONF_SLCD_PVAL 0 104 #define CONF_SLCD_CKDIV 7 105 106 /** Internal/External VLCD selection. 107 * 0 : Internal VLCD generation 108 * 1 : External VLCD generation 109 */ 110 #define CONF_SLCD_VLCD_SEL 0 111 112 /** Reference fefresh frequency. 113 * 0: Bias Reference refresh frequency is 2KHz 114 * 1: Bias Reference refresh frequency is 1KHz 115 * 2: Bias Reference refresh frequency is 500Hz 116 * 3: Bias Reference refresh frequency is 250Hz 117 * 4: Bias Reference refresh frequency is 125Hz 118 * 5: Bias Reference refresh frequency is 62.5Hz 119 */ 120 #define CONF_SLCD_REF_REFRESH_FREQ 0 121 122 /** Power fefresh frequency. 123 * 0: Charge pump refresh frequency is 2KHz 124 * 1: Charge pump refresh frequency is 1KHz 125 * 2: Charge pump refresh frequency is 500Hz 126 * 3: Charge pump refresh frequency is 250Hz 127 */ 128 #define CONF_SLCD_POWER_REFRESH_FREQ 0 129 130 /** LCD Working Power Mode. 131 * 0:LCD power automatically select regualation mode or pump mode. 132 * 1:LCD power use step-up pump loop only. 133 * 2:LCD power use step-down drop-out regulation loop only. 134 */ 135 #define CONF_SLCD_POWER_MODE 0 136 137 /** COM/SEG PIN Selection. 138 * There are 52 LCD pins, but SLCD can drive up to 48 LCD pins which can be 139 * individually enabled or disabled according to the LCD glass. The number of LCD pins 140 * enabled should not be higher than the maximum of COM and SEG lines supported. 141 * COM and SEG lines are always assigned in ascending order. 142 * CONF_SLCD_PIN_L_MASK is pin mask [31,0] 143 * CONF_SLCD_PIN_H_MASK is pin mask [51,32] 144 */ 145 #define CONF_SLCD_PIN_L_MASK 0xffffffff 146 #define CONF_SLCD_PIN_H_MASK 0xfffff 147 #endif 148