1 #include "bflb_core.h"
2 #include "bl602_irq.h"
3 #include "bl602_memorymap.h"
4
5 #define DMA_CHANNEL_OFFSET 0x100
6
7 struct bflb_device_s bl602_device_table[] = {
8 { .name = "adc",
9 .reg_base = AON_BASE,
10 .irq_num = BL602_IRQ_GPADC_DMA,
11 .idx = 0,
12 .sub_idx = 0,
13 .dev_type = BFLB_DEVICE_TYPE_ADC,
14 .user_data = NULL },
15 { .name = "dac",
16 .reg_base = GLB_BASE,
17 .irq_num = 0xff,
18 .idx = 0,
19 .sub_idx = 0,
20 .dev_type = BFLB_DEVICE_TYPE_DAC,
21 .user_data = NULL },
22 { .name = "ef_ctrl",
23 .reg_base = EF_CTRL_BASE,
24 .irq_num = 0xff,
25 .idx = 0,
26 .sub_idx = 0,
27 .dev_type = BFLB_DEVICE_TYPE_EF_CTRL,
28 .user_data = NULL },
29 { .name = "gpio",
30 .reg_base = GLB_BASE,
31 .irq_num = BL602_IRQ_GPIO_INT0,
32 .idx = 0,
33 .sub_idx = 0,
34 .dev_type = BFLB_DEVICE_TYPE_GPIO,
35 .user_data = NULL },
36 { .name = "uart0",
37 .reg_base = UART0_BASE,
38 .irq_num = BL602_IRQ_UART0,
39 .idx = 0,
40 .dev_type = BFLB_DEVICE_TYPE_UART,
41 .user_data = NULL },
42 { .name = "uart1",
43 .reg_base = UART1_BASE,
44 .irq_num = BL602_IRQ_UART1,
45 .idx = 1,
46 .dev_type = BFLB_DEVICE_TYPE_UART,
47 .user_data = NULL },
48 { .name = "spi0",
49 .reg_base = SPI_BASE,
50 .irq_num = BL602_IRQ_SPI0,
51 .idx = 0,
52 .dev_type = BFLB_DEVICE_TYPE_SPI,
53 .user_data = NULL },
54 { .name = "pwm0",
55 .reg_base = PWM_BASE,
56 .irq_num = BL602_IRQ_PWM,
57 .idx = 0,
58 .dev_type = BFLB_DEVICE_TYPE_PWM,
59 .user_data = NULL },
60 { .name = "dma0_ch0",
61 .reg_base = DMA_BASE + 1 * DMA_CHANNEL_OFFSET,
62 .irq_num = BL602_IRQ_DMA0_ALL,
63 .idx = 0,
64 .sub_idx = 0,
65 .dev_type = BFLB_DEVICE_TYPE_DMA,
66 .user_data = NULL },
67 { .name = "dma0_ch1",
68 .reg_base = DMA_BASE + 2 * DMA_CHANNEL_OFFSET,
69 .irq_num = BL602_IRQ_DMA0_ALL,
70 .idx = 0,
71 .sub_idx = 1,
72 .dev_type = BFLB_DEVICE_TYPE_DMA,
73 .user_data = NULL },
74 { .name = "dma0_ch2",
75 .reg_base = DMA_BASE + 3 * DMA_CHANNEL_OFFSET,
76 .irq_num = BL602_IRQ_DMA0_ALL,
77 .idx = 0,
78 .sub_idx = 2,
79 .dev_type = BFLB_DEVICE_TYPE_DMA,
80 .user_data = NULL },
81 { .name = "dma0_ch3",
82 .reg_base = DMA_BASE + 4 * DMA_CHANNEL_OFFSET,
83 .irq_num = BL602_IRQ_DMA0_ALL,
84 .idx = 0,
85 .sub_idx = 3,
86 .dev_type = BFLB_DEVICE_TYPE_DMA,
87 .user_data = NULL },
88 { .name = "dma0_ch4",
89 .reg_base = DMA_BASE + 5 * DMA_CHANNEL_OFFSET,
90 .irq_num = BL602_IRQ_DMA0_ALL,
91 .idx = 0,
92 .sub_idx = 4,
93 .dev_type = BFLB_DEVICE_TYPE_DMA,
94 .user_data = NULL },
95 { .name = "dma0_ch5",
96 .reg_base = DMA_BASE + 6 * DMA_CHANNEL_OFFSET,
97 .irq_num = BL602_IRQ_DMA0_ALL,
98 .idx = 0,
99 .sub_idx = 5,
100 .dev_type = BFLB_DEVICE_TYPE_DMA,
101 .user_data = NULL },
102 { .name = "dma0_ch6",
103 .reg_base = DMA_BASE + 7 * DMA_CHANNEL_OFFSET,
104 .irq_num = BL602_IRQ_DMA0_ALL,
105 .idx = 0,
106 .sub_idx = 6,
107 .dev_type = BFLB_DEVICE_TYPE_DMA,
108 .user_data = NULL },
109 { .name = "dma0_ch7",
110 .reg_base = DMA_BASE + 8 * DMA_CHANNEL_OFFSET,
111 .irq_num = BL602_IRQ_DMA0_ALL,
112 .idx = 0,
113 .sub_idx = 7,
114 .dev_type = BFLB_DEVICE_TYPE_DMA,
115 .user_data = NULL },
116 { .name = "i2c0",
117 .reg_base = I2C_BASE,
118 .irq_num = BL602_IRQ_I2C0,
119 .idx = 0,
120 .sub_idx = 0,
121 .dev_type = BFLB_DEVICE_TYPE_I2C,
122 .user_data = NULL },
123 { .name = "timer0",
124 .reg_base = TIMER_BASE,
125 .irq_num = BL602_IRQ_TIMER0,
126 .idx = 0,
127 .sub_idx = 0,
128 .dev_type = BFLB_DEVICE_TYPE_TIMER,
129 .user_data = NULL },
130 { .name = "timer1",
131 .reg_base = TIMER_BASE,
132 .irq_num = BL602_IRQ_TIMER1,
133 .idx = 1,
134 .sub_idx = 0,
135 .dev_type = BFLB_DEVICE_TYPE_TIMER,
136 .user_data = NULL },
137 { .name = "rtc",
138 .reg_base = HBN_BASE,
139 .irq_num = BL602_IRQ_HBN_OUT0,
140 .idx = 0,
141 .sub_idx = 0,
142 .dev_type = BFLB_DEVICE_TYPE_RTC,
143 .user_data = NULL },
144 { .name = "aes",
145 .reg_base = SEC_ENG_BASE,
146 .irq_num = 0xff,
147 .idx = 0,
148 .sub_idx = 0,
149 .dev_type = BFLB_DEVICE_TYPE_AES,
150 .user_data = NULL },
151 { .name = "sha",
152 .reg_base = SEC_ENG_BASE,
153 .irq_num = 0xff,
154 .idx = 0,
155 .sub_idx = 0,
156 .dev_type = BFLB_DEVICE_TYPE_SHA,
157 .user_data = NULL },
158 { .name = "trng",
159 .reg_base = SEC_ENG_BASE,
160 .irq_num = 0xff,
161 .idx = 0,
162 .sub_idx = 0,
163 .dev_type = BFLB_DEVICE_TYPE_TRNG,
164 .user_data = NULL },
165 { .name = "pka",
166 .reg_base = SEC_ENG_BASE,
167 .irq_num = 0xff,
168 .idx = 0,
169 .sub_idx = 0,
170 .dev_type = BFLB_DEVICE_TYPE_PKA,
171 .user_data = NULL },
172 { .name = "watchdog",
173 .reg_base = TIMER_BASE,
174 .irq_num = BL602_IRQ_WDT,
175 .idx = 0,
176 .sub_idx = 0,
177 .dev_type = BFLB_DEVICE_TYPE_TIMER,
178 .user_data = NULL },
179 { .name = "irtx",
180 .reg_base = IR_BASE,
181 .irq_num = BL602_IRQ_IRTX,
182 .idx = 0,
183 .sub_idx = 0,
184 .dev_type = BFLB_DEVICE_TYPE_IR,
185 .user_data = NULL },
186 { .name = "irrx",
187 .reg_base = IR_BASE,
188 .irq_num = BL602_IRQ_IRRX,
189 .idx = 0,
190 .sub_idx = 0,
191 .dev_type = BFLB_DEVICE_TYPE_IR,
192 .user_data = NULL },
193 { .name = "sdio2",
194 .reg_base = SDU_BASE,
195 .irq_num = BL602_IRQ_SDIO,
196 .idx = 0,
197 .sub_idx = 0,
198 .dev_type = BFLB_DEVICE_TYPE_SDIO2,
199 .user_data = NULL },
200 };
201
bflb_device_get_by_name(const char * name)202 struct bflb_device_s *bflb_device_get_by_name(const char *name)
203 {
204 for (uint8_t i = 0; i < sizeof(bl602_device_table) / sizeof(bl602_device_table[0]); i++) {
205 if (strcmp(bl602_device_table[i].name, name) == 0) {
206 return &bl602_device_table[i];
207 }
208 }
209 return NULL;
210 }
211
bflb_device_get_by_id(uint8_t type,uint8_t idx)212 struct bflb_device_s *bflb_device_get_by_id(uint8_t type, uint8_t idx)
213 {
214 for (uint8_t i = 0; i < sizeof(bl602_device_table) / sizeof(bl602_device_table[0]); i++) {
215 if ((bl602_device_table[i].dev_type == type) && (bl602_device_table[i].idx = idx)) {
216 return &bl602_device_table[i];
217 }
218 }
219 return NULL;
220 }
221
bflb_device_set_userdata(struct bflb_device_s * device,void * user_data)222 void bflb_device_set_userdata(struct bflb_device_s *device, void *user_data)
223 {
224 device->user_data = user_data;
225 }