1 /* 2 * Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_ 18 #define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_ 19 20 #include "core-v-mcu-properties.h" 21 /* Memories */ 22 /* FC memory. */ 23 #define FC_TCDM_ADDR (0x1B000000) 24 #if (ARCHI_HAS_FC_ALIAS) 25 #define FC_TCDM_ADDR_ALIAS (0x00000000) 26 #endif /* ARCHI_HAS_FC_ALIAS */ 27 28 /* L2 memory */ 29 #define L2_SHARED_ADDR (0x1C000000) 30 #if (ARCHI_HAS_L2_ALIAS) 31 #define L2_SHARED_ADDR_ALIAS (0x00000000) 32 #endif /* ARCHI_HAS_L2_ALIAS */ 33 34 /* L1 cluster memory */ 35 #define CL_L1_ADDR (0x10000000) 36 #if (ARCHI_HAS_CL_L1_ALIAS) 37 #define CL_L1_ADDR_ALIAS (0x00000000) 38 #endif /* ARCHI_HAS_CL_L1_ALIAS */ 39 40 /* L1 cluster TS */ 41 #if (ARCHI_HAS_CL_L1_TS) 42 #define L2_PRIV0_TS_ADDR (0x10100000) 43 #endif /* ARCHI_HAS_CL_L1_TS */ 44 45 /* ROM memory (8 KiB)*/ 46 #define ROM_ADDR (0x1A000000) 47 #define ROM_SIZE (0x00002000) 48 49 /* Cluster */ 50 #define ARCHI_CLUSTER_ADDR (0x00000000) 51 #define ARCHI_CLUSTER_SIZE (0x00400000) 52 #define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE) 53 #define ARCHI_CLUSTER_PERIPHERALS_OFFSET (0x00200000) 54 55 /* Cluster peripherals */ 56 #define ARCHI_TIMER_SIZE (0x00000800) 57 58 #define ARCHI_CLUSTER_CTRL_OFFSET (0x00000000) 59 #define ARCHI_TIMER_OFFSET (0x00000400) 60 #define ARCHI_EU_OFFSET (0x00000800) 61 #define ARCHI_HWCE_OFFSET (0x00001000) 62 #define ARCHI_ICACHE_CTRL_OFFSET (0x00001400) 63 #define ARCHI_MCHAN_EXT_OFFSET (0x00001800) 64 65 #define ARCHI_CLUSTER_PERIPHERALS_ADDR (ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET) 66 #define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) (ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET) 67 68 #define ARCHI_CLUSTER_CTRL_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_CLUSTER_CTRL_OFFSET) 69 #define ARCHI_CLUSTER_TIMER_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_TIMER_OFFSET) 70 #define ARCHI_ICACHE_CTRL_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_ICACHE_CTRL_OFFSET) 71 #define ARCHI_EU_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_EU_OFFSET) 72 #define ARCHI_HWCE_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_HWCE_OFFSET) 73 #define ARCHI_MCHAN_EXT_ADDR (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_MCHAN_EXT_OFFSET) 74 75 #define ARCHI_DEMUX_PERIPHERALS_OFFSET (0x204000) 76 #define ARCHI_EU_DEMUX_OFFSET (0x00000) 77 #define ARCHI_MCHAN_DEMUX_OFFSET (0x00400) 78 79 #define ARCHI_DEMUX_PERIPHERALS_ADDR (ARCHI_CLUSTER_GLOBAL_ADDR(0) + ARCHI_DEMUX_PERIPHERALS_OFFSET) 80 #define ARCHI_EU_DEMUX_ADDR (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET) 81 #define ARCHI_MCHAN_DEMUX_ADDR (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET) 82 83 84 /* SoC peripherals */ 85 #define SOC_PERIPHERALS_ADDR (0x1A100000) 86 87 #define SOC_FLL_OFFSET (0x00000000) 88 #define CL_FLL_OFFSET (0x00000800) 89 #define GPIO_OFFSET (0x00001000) 90 #define UDMA_OFFSET (0x00002000) 91 #define APB_SOC_CTRL_OFFSET (0x00004000) 92 #define ADV_TIMER_OFFSET (0x00005000) /* PWM. */ 93 #define SOC_EU_OFFSET (0x00006000) 94 #define FC_IRQ_OFFSET (0x00009800) 95 /* #define FC_IRQ_OFFSET (0x00009000) */ /* valid mirror address */ 96 #define FC_TIMER_OFFSET (0x0000B000) 97 #define FC_HWPE_OFFSET (0x0000C000) 98 #define STDOUT_OFFSET (0x0000F000) 99 #define DEBUG_OFFSET (0x00010000) 100 101 #define SOC_FLL_ADDR (SOC_PERIPHERALS_ADDR + SOC_FLL_OFFSET) 102 #define CL_FLL_ADDR (SOC_PERIPHERALS_ADDR + CL_FLL_OFFSET) 103 #define GPIO_ADDR (SOC_PERIPHERALS_ADDR + GPIO_OFFSET) 104 #define UDMA_CTRL_ADDR (SOC_PERIPHERALS_ADDR + UDMA_OFFSET) 105 #define APB_SOC_CTRL_ADDR (SOC_PERIPHERALS_ADDR + APB_SOC_CTRL_OFFSET) 106 #define ADV_TIMER_ADDR (SOC_PERIPHERALS_ADDR + ADV_TIMER_OFFSET) 107 #define SOC_EU_ADDR (SOC_PERIPHERALS_ADDR + SOC_EU_OFFSET) 108 #define FC_IRQ_ADDR (SOC_PERIPHERALS_ADDR + FC_IRQ_OFFSET) 109 #define FC_TIMER_ADDR (SOC_PERIPHERALS_ADDR + FC_TIMER_OFFSET) 110 #define FC_HWPE_ADDR (SOC_PERIPHERALS_ADDR + FC_HWPE_OFFSET) 111 #define STDOUT_ADDR (SOC_PERIPHERALS_ADDR + STDOUT_OFFSET) 112 #define DEBUG_ADDR (SOC_PERIPHERALS_ADDR + DEBUG_OFFSET) 113 114 /* UDMA peripherals */ 115 /* #define UDMA_GC_ADDR (UDMA_CTRL_ADDR + 0x780) */ 116 /* UDMA base peripheral addr = UDMA base address + UDMA ctrl. */ 117 #define UDMA_PERIPH_BASE_ADDR (UDMA_CTRL_ADDR + 0x80) 118 #define UDMA_SPIM(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_SPIM_ID(id) << UDMA_PERIPH_SIZE_LOG2)) 119 #define UDMA_HYPER(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_HYPER_ID(id) << UDMA_PERIPH_SIZE_LOG2)) 120 #define UDMA_UART(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_UART_ID(id) << UDMA_PERIPH_SIZE_LOG2)) 121 #define UDMA_I2C(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_I2C_ID(id) << UDMA_PERIPH_SIZE_LOG2)) 122 #define UDMA_DMACPY(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_DMACPY_ID(id) << UDMA_PERIPH_SIZE_LOG2)) 123 #define UDMA_I2S(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_I2S_ID(id) << UDMA_PERIPH_SIZE_LOG2)) 124 #define UDMA_CPI(id) (UDMA_PERIPH_BASE_ADDR + (UDMA_CPI_ID(id) << UDMA_PERIPH_SIZE_LOG2)) 125 126 #endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_ */ 127