1 /*
2  * Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *     http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
18 #define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
19 
20 /* PULP defs */
21 #define PULP
22 
23 #define ARCHI_FPGA_FREQUENCY 5000000
24 
25 /* hardware modules */
26 #define ARCHI_NUM_TIMER 1
27 #define ARCHI_NUM_FLL 2
28 
29 #define ARCHI_REF_CLOCK_LOG2 15
30 #define ARCHI_REF_CLOCK	(1 << ARCHI_REF_CLOCK_LOG2)
31 
32 #define ARCHI_NB_FLL	  3
33 
34 #define __RT_FLL_CL	2
35 #define __RT_FLL_PERIPH 1
36 #define __RT_FLL_FC	0
37 
38 #define __RT_FREQ_DOMAIN_FC	0
39 #define __RT_FREQ_DOMAIN_CL	2
40 #define __RT_FREQ_DOMAIN_PERIPH 1
41 #define RT_FREQ_NB_DOMAIN	3
42 
43 /* Cores & cluster */
44 /* FC */
45 #define ARCHI_FC_CID                (32)
46 
47 /* Cluster */
48 #define ARCHI_HAS_CLUSTER           (1)
49 #define ARCHI_CL_CID(id)            (id)
50 #define ARCHI_CLUSTER_NB_PE         (8) /* Processing elements. */
51 
52 /* Memories */
53 /* FC memory */
54 #define ARCHI_HAS_FC_TCDM           (1)
55 #define ARCHI_HAS_FC_ALIAS          (1)
56 #define FC_TCDM_SIZE                (0x00004000) /* 16kB. */
57 
58 /* L2 memory */
59 #define ARCHI_HAS_L2_ALIAS          (0)
60 #define L2_SHARED_SIZE              (0x00080000) /* 512kB. */
61 
62 /* L1 cluster memory */
63 #define ARCHI_HAS_CL_L1_ALIAS       (1)
64 #define CL_L1_SIZE                  (0x00010000) /* 64kB. */
65 
66 /* L1 cluster TS */
67 #define ARCHI_HAS_CL_L1_TS          (1)
68 
69 #define UDMA_NB_PERIPH              (10)
70 /* Size of each UDMA peripheral */
71 #define UDMA_PERIPH_SIZE_LOG2       (7)
72 #define UDMA_PERIPH_SIZE            (1 << UDMA_PERIPH_SIZE_LOG2)
73 
74 #endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_ */
75