1 /* 2 * Copyright (C) 2019 ETH Zurich and University of Bologna 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 * 16 * SPDX-License-Identifier: Apache-2.0 17 * Author: Robert Balas (balasr@iis.ee.ethz.ch) 18 */ 19 20 #ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_ 21 #define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_ 22 23 /* 24 * SOC PERIPHERALS 25 */ 26 27 #define PULP_SOC_PERIPHERALS_ADDR 0x1A100000 28 29 #define PULP_FC_TIMER_SIZE 0x00000800 30 31 #define PULP_FLL_OFFSET 0x00000000 32 #define PULP_GPIO_OFFSET 0x00001000 33 #define PULP_UDMA_OFFSET 0x00002000 34 #define PULP_APB_SOC_CTRL_OFFSET 0x00004000 35 #define PULP_ADV_TIMER_OFFSET 0x00005000 36 #define PULP_SOC_EU_OFFSET 0x00006000 37 #define PULP_FC_IRQ_OFFSET 0x00009800 38 /* #define PULP_FC_IRQ_OFFSET 0x00009000 */ /* this is a mirror of above */ 39 #define PULP_FC_TIMER_OFFSET 0x0000B000 40 #define PULP_FC_HWPE_OFFSET 0x0000C000 41 #define PULP_STDOUT_OFFSET 0x0000F000 42 #define PULP_DEBUG_OFFSET 0x00010000 43 44 #define PULP_FLL_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FLL_OFFSET) 45 #define PULP_GPIO_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_GPIO_OFFSET) 46 #define PULP_UDMA_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_UDMA_OFFSET) 47 #define PULP_APB_SOC_CTRL_ADDR \ 48 (PULP_SOC_PERIPHERALS_ADDR + PULP_APB_SOC_CTRL_OFFSET) 49 #define PULP_ADV_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_ADV_TIMER_OFFSET) 50 #define PULP_SOC_EU_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_SOC_EU_OFFSET) 51 #define PULP_FC_IRQ_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_IRQ_OFFSET) 52 /* #define PULP_FC_ITC_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_ITC_OFFSET) */ 53 #define PULP_FC_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_TIMER_OFFSET) 54 #define PULP_FC_HWPE_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_HWPE_OFFSET) 55 #define PULP_STDOUT_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_STDOUT_OFFSET) 56 57 #define PULP_FLL_AREA_SIZE 0x00000010 58 59 /* 60 * CLUSTER 61 */ 62 63 #define PULP_CLUSTER_ADDR 0x00000000 64 #define PULP_CLUSTER_SIZE 0x00400000 65 #define PULP_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*PULP_CLUSTER_SIZE) 66 67 /* 68 * CLUSTER PERIPHERALS 69 */ 70 71 #define PULP_CLUSTER_PERIPHERALS_OFFSET 0x00200000 72 73 #define PULP_TIMER_OFFSET 0x00000400 74 75 #define PULP_CLUSTER_PERIPHERALS_ADDR \ 76 (PULP_CLUSTER_ADDR + PULP_CLUSTER_PERIPHERALS_OFFSET) 77 #define PULP_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) \ 78 (PULP_CLUSTER_GLOBAL_ADDR(cid) + PULP_CLUSTER_PERIPHERALS_OFFSET) 79 80 #endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_ */ 81