1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 */ 9 #ifndef __RT_HW_CPU_H__ 10 #define __RT_HW_CPU_H__ 11 12 #include <rtdef.h> 13 #include <cpuport.h> 14 #include <mm_aspace.h> 15 16 #ifdef RT_USING_OFW 17 #include <drivers/ofw.h> 18 #endif 19 20 #define ID_ERROR __INT64_MAX__ 21 #define MPIDR_AFFINITY_MASK 0x000000ff00ffffffUL 22 23 struct cpu_ops_t 24 { 25 const char *method; 26 int (*cpu_init)(rt_uint32_t id, void *param); 27 int (*cpu_boot)(rt_uint32_t id, rt_uint64_t entry); 28 void (*cpu_shutdown)(void); 29 }; 30 #define sysreg_32(op1, crn, crm, op2) s3_##op1 ##_##crn ##_##crm ##_##op2 31 #define sysreg_64(op1, crn, crm, op2) sysreg_32(op1, crn, crm, op2) 32 33 #define MPIDR_AFFINITY_MASK 0x000000ff00ffffffUL 34 35 #define MPIDR_LEVEL_BITS_SHIFT 3 36 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT) 37 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) 38 #define MPIDR_LEVEL_SHIFT(level) (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT) 39 40 #define MPIDR_AFFINITY_LEVEL(mpidr, level) (((mpidr) >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) 41 42 /* GIC registers */ 43 #define ICC_IAR0_SYS sysreg_64(0, c12, c8, 0) 44 #define ICC_IAR1_SYS sysreg_64(0, c12, c12, 0) 45 #define ICC_EOIR0_SYS sysreg_64(0, c12, c8, 1) 46 #define ICC_EOIR1_SYS sysreg_64(0, c12, c12, 1) 47 #define ICC_HPPIR0_SYS sysreg_64(0, c12, c8, 2) 48 #define ICC_HPPIR1_SYS sysreg_64(0, c12, c12, 2) 49 #define ICC_BPR0_SYS sysreg_64(0, c12, c8, 3) 50 #define ICC_BPR1_SYS sysreg_64(0, c12, c12, 3) 51 #define ICC_DIR_SYS sysreg_64(0, c12, c11, 1) 52 #define ICC_PMR_SYS sysreg_64(0, c4, c6, 0) 53 #define ICC_RPR_SYS sysreg_64(0, c12, c11, 3) 54 #define ICC_CTLR_SYS sysreg_64(0, c12, c12, 4) 55 #define ICC_SRE_SYS sysreg_64(0, c12, c12, 5) 56 #define ICC_IGRPEN0_SYS sysreg_64(0, c12, c12, 6) 57 #define ICC_IGRPEN1_SYS sysreg_64(0, c12, c12, 7) 58 #define ICC_SGI0R_SYS sysreg_64(0, c12, c11, 7) 59 #define ICC_SGI1R_SYS sysreg_64(0, c12, c11, 5) 60 #define ICC_ASGI1R_SYS sysreg_64(0, c12, c11, 6) 61 62 /* Arch timer registers */ 63 #define CNTP_CTL CNTP_CTL_EL0 /* EL1 Physical Timer */ 64 #define CNTHP_CTL CNTHP_CTL_EL2 /* EL2 Non-secure Physical Timer */ 65 #define CNTHPS_CTL CNTHPS_CTL_EL2 /* EL2 Secure Physical Timer */ 66 #define CNTPS_CTL CNTPS_CTL_EL1 /* EL3 Physical Timer */ 67 #define CNTV_CTL CNTV_CTL_EL0 /* EL1 Virtual Timer */ 68 #define CNTHV_CTL CNTHV_CTL_EL2 /* EL2 Non-secure Virtual Timer */ 69 #define CNTHVS_CTL CNTHVS_CTL_EL2 /* EL2 Secure Virtual Timer */ 70 71 #define CNTP_CVAL CNTP_CVAL_EL0 72 #define CNTHP_CVAL CNTHP_CVAL_EL2 73 #define CNTHPS_CVAL CNTHPS_CVAL_EL2 74 #define CNTPS_CVAL CNTPS_CVAL_EL1 75 #define CNTV_CVAL CNTV_CVAL_EL0 76 #define CNTHV_CVAL CNTHV_CVAL_EL2 77 #define CNTHVS_CVAL CNTHVS_CVAL_EL2 78 79 #define CNTP_TVAL CNTP_TVAL_EL0 80 #define CNTHP_TVAL CNTHP_TVAL_EL2 81 #define CNTHPS_TVAL CNTHPS_TVAL_EL2 82 #define CNTPS_TVAL CNTPS_TVAL_EL1 83 #define CNTV_TVAL CNTV_TVAL_EL0 84 #define CNTHV_TVAL CNTHV_TVAL_EL2 85 #define CNTHVS_TVAL CNTHVS_TVAL_EL2 86 87 #define CNTPCT CNTPCT_EL0 88 #define CNTVCT CNTVCT_EL0 89 #define CNTFRQ CNTFRQ_EL0 90 extern rt_uint64_t rt_cpu_mpidr_table[]; 91 92 #endif /* __RT_HW_CPU_H__ */ 93