1 /*
2  * Allwinner SoCs display driver.
3  *
4  * Copyright (C) 2016 Allwinner.
5  *
6  * This file is licensed under the terms of the GNU General Public
7  * License version 2.  This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 
11 /*****************************************************************************
12  *  All Winner Tech, All Right Reserved. 2014-2015 Copyright (c)
13  *
14  *  File name   :       de_csc_type.h
15  *
16  *  Description :       display engine 2.0 csc struct declaration
17  *
18  *  History     :       2014/05/16  vito cheng  v0.1  Initial version
19 ****************************************************************************/
20 
21 #ifndef __DE_CSC_TYPE_H__
22 #define __DE_CSC_TYPE_H__
23 
24 union CSC_BYPASS_REG {
25     unsigned int dwval;
26     struct {
27         unsigned int enable:1;
28         unsigned int res0:31;
29     } bits;
30 };
31 
32 union CSC_BYPASS_REG2 {
33     unsigned int dwval;
34     struct {
35         unsigned int res0:1;
36         unsigned int enable:1;
37         unsigned int res1:30;
38     } bits;
39 };
40 
41 union CSC_COEFF_REG {
42     unsigned int dwval;
43     struct {
44         unsigned int coeff:13;
45         unsigned int res0:19;
46     } bits;
47 };
48 
49 union CSC_CONST_REG {
50     unsigned int dwval;
51     struct {
52         unsigned int cnst:20;
53         unsigned int res0:12;
54     } bits;
55 };
56 
57 union CSC_CONST_REG2 {
58     unsigned int dwval;
59     struct {
60         unsigned int cnst:14;
61         unsigned int res0:18;
62     } bits;
63 };
64 
65 union GLB_ALPHA_REG {
66     unsigned int dwval;
67     struct {
68         unsigned int cnst:24;
69         unsigned int alpha:8;
70     } bits;
71 };
72 
73 /* Channel CSC and Device CSC */
74 struct __csc_reg_t {
75     union CSC_BYPASS_REG bypass;
76     unsigned int res[3];
77     union CSC_COEFF_REG c00;
78     union CSC_COEFF_REG c01;
79     union CSC_COEFF_REG c02;
80     union CSC_CONST_REG c03;
81     union CSC_COEFF_REG c10;
82     union CSC_COEFF_REG c11;
83     union CSC_COEFF_REG c12;
84     union CSC_CONST_REG c13;
85     union CSC_COEFF_REG c20;
86     union CSC_COEFF_REG c21;
87     union CSC_COEFF_REG c22;
88     union CSC_CONST_REG c23;
89     union GLB_ALPHA_REG alpha;
90 };
91 
92 /* CSC IN SMBL */
93 struct __csc2_reg_t {
94     union CSC_BYPASS_REG2 bypass;
95     unsigned int res[31];
96     union CSC_COEFF_REG c00;
97     union CSC_COEFF_REG c01;
98     union CSC_COEFF_REG c02;
99     union CSC_CONST_REG2 c03;
100     union CSC_COEFF_REG c10;
101     union CSC_COEFF_REG c11;
102     union CSC_COEFF_REG c12;
103     union CSC_CONST_REG2 c13;
104     union CSC_COEFF_REG c20;
105     union CSC_COEFF_REG c21;
106     union CSC_COEFF_REG c22;
107     union CSC_CONST_REG2 c23;
108 };
109 
110 /* Input CSC in FCE */
111 struct __icsc_reg_t {
112     union CSC_BYPASS_REG bypass;
113 };
114 #endif
115