1 /*
2  * Allwinner SoCs display driver.
3  *
4  * Copyright (C) 2016 Allwinner.
5  *
6  * This file is licensed under the terms of the GNU General Public
7  * License version 2.  This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 
11 /**
12  *  All Winner Tech, All Right Reserved. 2014-2015 Copyright (c)
13  *
14  *  File name   :       de_gsu_type.h
15  *
16  *  Description :       display engine 2.0 gsu struct declaration
17  *
18  *  History     :       2014/03/20  vito cheng  v0.1  Initial version
19  *
20  */
21 
22 #ifndef __DE_GSU_TYPE_H__
23 #define __DE_GSU_TYPE_H__
24 
25 /*
26  * __gsu_reg_t
27  */
28 union GSU_CTRL_REG {
29     unsigned int dwval;
30     struct {
31         unsigned int en:1;
32         unsigned int res0:3;
33         unsigned int coef_switch_rdy:1;
34         unsigned int res1:25;
35         unsigned int reset:1;
36         unsigned int res2:1;
37     } bits;
38 };
39 
40 union GSU_STATUS_REG {
41     unsigned int dwval;
42     struct {
43         unsigned int res0:4;
44         unsigned int busy:1;
45         unsigned int res1:11;
46         unsigned int line_cnt:12;
47         unsigned int res2:4;
48     } bits;
49 };
50 
51 union GSU_FIELD_CTRL_REG {
52     unsigned int dwval;
53     struct {
54         unsigned int vphase_sel_en:1;
55         unsigned int res0:31;
56     } bits;
57 };
58 
59 union GSU_BIST_REG {
60     unsigned int dwval;
61     struct {
62         unsigned int bist_en:1;
63         unsigned int res0:15;
64         unsigned int bist_sel:5;
65         unsigned int res1:11;
66     } bits;
67 };
68 
69 union GSU_OUTSIZE_REG {
70     unsigned int dwval;
71     struct {
72         unsigned int width:13;
73         unsigned int res0:3;
74         unsigned int height:13;
75         unsigned int res1:3;
76     } bits;
77 };
78 
79 union GSU_INSIZE_REG {
80     unsigned int dwval;
81     struct {
82         unsigned int width:13;
83         unsigned int res0:3;
84         unsigned int height:13;
85         unsigned int res1:3;
86     } bits;
87 };
88 
89 union GSU_HSTEP_REG {
90     unsigned int dwval;
91     struct {
92         unsigned int res0:2;
93         unsigned int frac:18;
94         unsigned int integer:5;
95         unsigned int res1:7;
96     } bits;
97 };
98 
99 union GSU_VSTEP_REG {
100     unsigned int dwval;
101     struct {
102         unsigned int res0:2;
103         unsigned int frac:18;
104         unsigned int integer:5;
105         unsigned int res1:7;
106     } bits;
107 };
108 
109 union GSU_HPHASE_REG {
110     unsigned int dwval;
111     struct {
112         unsigned int res0:2;
113         unsigned int frac:18;
114         unsigned int integer:5;
115         unsigned int res1:7;
116     } bits;
117 };
118 
119 union GSU_VPHASE0_REG {
120     unsigned int dwval;
121     struct {
122         unsigned int res0:2;
123         unsigned int frac:18;
124         unsigned int integer:5;
125         unsigned int res1:7;
126     } bits;
127 };
128 
129 union GSU_VPHASE1_REG {
130     unsigned int dwval;
131     struct {
132         unsigned int res0:2;
133         unsigned int frac:18;
134         unsigned int integer:4;
135         unsigned int res1:8;
136     } bits;
137 };
138 
139 union GSU_HCOEFF_REG {
140     unsigned int dwval;
141     struct {
142         unsigned int coef0:8;
143         unsigned int coef1:8;
144         unsigned int coef2:8;
145         unsigned int coef3:8;
146     } bits;
147 };
148 
149 struct __gsu_reg_t {
150     union GSU_CTRL_REG ctrl;        /* 0x0000 */
151     unsigned int res0;      /* 0x0004 */
152     union GSU_STATUS_REG status;        /* 0x0008 */
153     union GSU_FIELD_CTRL_REG field; /* 0x000c */
154     union GSU_BIST_REG bist;        /* 0x0010 */
155     unsigned int res1[11];      /* 0x0014-3c */
156     union GSU_OUTSIZE_REG outsize;  /* 0x0040 */
157     unsigned int res5[15];      /* 0x0044-0x07c */
158     union GSU_INSIZE_REG insize;        /* 0x0080 */
159     unsigned int res2;      /* 0x0084 */
160     union GSU_HSTEP_REG hstep;      /* 0x0088 */
161     union GSU_VSTEP_REG vstep;      /* 0x008C */
162     union GSU_HPHASE_REG hphase;        /* 0x0090 */
163     unsigned int res3;      /* 0x0094 */
164     union GSU_VPHASE0_REG vphase0;  /* 0x0098 */
165     union GSU_VPHASE1_REG vphase1;  /* 0x009c */
166     unsigned int res4[88];      /* 0x00a0-1fc */
167     union GSU_HCOEFF_REG hcoeff[16];    /* 0x0200-0x23c */
168 };
169 
170 #endif
171