1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2016 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef __DE_LCD_H_ 12 #define __DE_LCD_H_ 13 14 #include "../include.h" 15 #include "de_feat.h" 16 17 enum __lcd_irq_id_t { 18 LCD_IRQ_TCON0_VBLK = 15, 19 LCD_IRQ_TCON1_VBLK = 14, 20 LCD_IRQ_TCON0_LINE = 13, 21 LCD_IRQ_TCON1_LINE = 12, 22 LCD_IRQ_TCON0_TRIF = 11, 23 LCD_IRQ_TCON0_CNTR = 10, 24 LCD_IRQ_FSYNC_INT = 9, 25 LCD_IRQ_DATA_EN_INT = 8, 26 }; 27 28 enum __dsi_irq_id_t { 29 DSI_IRQ_VIDEO_LINE = 3, 30 DSI_IRQ_VIDEO_VBLK = 2, 31 DSI_IRQ_INSTR_STEP = 1, 32 DSI_IRQ_INSTR_END = 0, 33 }; 34 35 enum __edp_irq_id_t { 36 EDP_IRQ_VBLK = 0, 37 EDP_IRQ_LINE1 = 1, 38 }; 39 40 enum __lcd_src_t { 41 LCD_SRC_DE = 0, 42 LCD_SRC_COLOR_BAR = 1, 43 LCD_SRC_GRAYSCALE = 2, 44 LCD_SRC_BLACK_BY_WHITE = 3, 45 LCD_SRC_BLACK = 4, 46 LCD_SRC_WHITE = 5, 47 LCD_SRC_GRID = 7, 48 LCD_SRC_BLUE = 8 49 }; 50 51 enum __tv_set_t { 52 TV_TO_GPIO = 1, 53 LCD_TO_GPIO = 0, 54 TV_CLK_F_CCU = 0, 55 TV_CLK_F_TVE = 1 56 }; 57 58 enum __de_perh_t { 59 LCD0 = 0, 60 LCD1 = 1, 61 TV0 = 2, 62 TV1 = 3 63 }; 64 65 s32 tcon0_out_to_gpio(u32 sel); 66 s32 tcon1_out_to_gpio(u32 sel); 67 s32 tcon1_tv_clk_enable(u32 sel, u32 en); 68 s32 tcon1_hdmi_clk_enable(u32 sel, u32 en); 69 s32 tcon0_dsi_clk_enable(u32 sel, u32 en); 70 s32 tcon_de_attach(u32 tcon_index, u32 de_index); 71 s32 tcon_get_attach_by_de_index(u32 de_index); 72 s32 tcon_top_set_reg_base(u32 sel, uintptr_t base); 73 uintptr_t tcon_top_get_reg_base(u32 sel); 74 s32 lvds_open(u32 sel, struct disp_panel_para *panel); 75 s32 lvds_close(u32 sel); 76 u32 tcon_get_cur_field(u32 sel, u32 tcon_index); 77 s32 tcon_irq_enable(u32 sel, enum __lcd_irq_id_t id); 78 s32 tcon_irq_disable(u32 sel, enum __lcd_irq_id_t id); 79 s32 tcon_set_reg_base(u32 sel, uintptr_t address); 80 uintptr_t tcon_get_reg_base(u32 sel); 81 s32 tcon_init(u32 sel); 82 s32 tcon_exit(u32 sel); 83 s32 tcon_get_timing(u32 sel, u32 index, struct disp_video_timings *tt); 84 u32 tcon_irq_query(u32 sel, enum __lcd_irq_id_t id); 85 u32 tcon_get_start_delay(u32 sel, u32 tcon_index); 86 u32 tcon_get_cur_line(u32 sel, u32 tcon_index); 87 s32 tcon_gamma(u32 sel, u32 en, u32 *gamma_tbl); 88 s32 tcon_get_status(u32 sel, u32 tcon_index); 89 90 s32 tcon0_cfg(u32 sel, struct disp_panel_para *panel); 91 s32 tcon0_cfg_ext(u32 sel, struct panel_extend_para *extend_panel); 92 s32 tcon0_src_select(u32 sel, enum __lcd_src_t src, u32 de_no); 93 s32 tcon0_src_get(u32 sel); 94 s32 tcon0_open(u32 sel, struct disp_panel_para *panel); 95 s32 tcon0_close(u32 sel); 96 s32 tcon0_set_dclk_div(u32 sel, u8 div); 97 u32 tcon0_get_dclk_div(u32 sel); 98 s32 tcon0_tri_busy(u32 sel); 99 s32 tcon0_cpu_set_auto_mode(u32 sel); 100 s32 tcon0_tri_start(u32 sel); 101 u32 tcon0_cpu_16b_to_24b(u32 value); 102 u32 tcon0_cpu_24b_to_16b(u32 value); 103 u32 tcon0_cpu_busy(u32 sel); 104 s32 tcon0_cpu_wr_24b(u32 sel, u32 index, u32 data); 105 s32 tcon0_cpu_wr_24b_index(u32 sel, u32 index); 106 s32 tcon0_cpu_wr_24b_data(u32 sel, u32 data); 107 s32 tcon0_cpu_rd_24b(u32 sel, u32 index, u32 *data); 108 s32 tcon0_cpu_rd_24b_data(u32 sel, u32 index, u32 *data, u32 size); 109 s32 tcon0_cpu_wr_16b(u32 sel, u32 index, u32 data); 110 s32 tcon0_cpu_wr_16b_index(u32 sel, u32 index); 111 s32 tcon0_cpu_wr_16b_data(u32 sel, u32 data); 112 s32 tcon0_cpu_rd_16b(u32 sel, u32 index, u32 *data); 113 114 s32 tcon_pan_sel(u32 sel, u32 pad); 115 s32 tcon1_open(u32 sel); 116 s32 tcon1_close(u32 sel); 117 s32 tcon1_src_select(u32 sel, enum __lcd_src_t src, enum __de_perh_t de_no); 118 s32 tcon1_src_get(u32 sel); 119 s32 tcon1_cfg_ex(u32 sel, struct disp_panel_para *panel); 120 s32 tcon1_set_timming(u32 sel, struct disp_video_timings *timming); 121 s32 tcon1_cfg(u32 sel, struct disp_video_timings *timing); 122 #ifdef TCON_POL_CORRECT 123 u32 tcon1_cfg_correct(u32 sel, struct disp_video_timings *timing); 124 #endif 125 s32 tcon1_set_tv_mode(u32 sel, enum disp_output_type mode); 126 s32 hmdi_src_sel(u32 sel); 127 s32 tcon1_hdmi_color_remap(u32 sel, u32 onoff, u32 is_yuv); 128 s32 tcon1_yuv_range(u32 sel, u32 onoff); 129 u32 tcon0_get_cpu_tri2_start_delay(u32 sel); 130 s32 tcon_set_sync_pol(u32 sel, u32 ver_pol, u32 hor_pol); 131 s32 get_tcon_type_by_de_index(u32 de_index); 132 s32 tcon_vdpo_clk_enable(u32 sel, u32 en); 133 s32 vdpo_src_sel(u32 sel, u32 src); 134 void tcon_show_builtin_patten(u32 sel, u32 patten); 135 void tcon0_cpu_wr_16b_multi(u32 sel, u8 cmd, u8 *para, u32 para_num); 136 void tcon0_cpu_wr_24b_multi(u32 sel, u8 cmd, u8 *para, u32 para_num); 137 138 /** 139 * @name :tcon_fsync_set_pol 140 * @brief :set fsync's polarity 141 * @param[IN] :sel:tcon index 142 * @param[IN] :pol:polarity. 1:positive;0:negetive 143 * positive: 144 * +---------+ 145 * ---------+ +----------- 146 * 147 * negative: 148 * ---------+ +------------ 149 * +---------+ 150 * 151 * @return :always 0 152 */ 153 s32 tcon_set_fsync_pol(u32 sel, u32 pol); 154 155 /** 156 * @name :tcon_set_fsync_active_time 157 * @brief :set tcon fsync's active time 158 * @param[IN] :sel:tcon index 159 * @param[IN] :pixel_num:number of pixel time(Tpixel) to set 160 * 161 * Tpixel = 1/fps*1e9/vt/ht, unit:ns 162 * 163 * @return :0 if success 164 */ 165 s32 tcon_set_fsync_active_time(u32 sel, u32 pixel_num); 166 167 void tcon_reset(u32 sel); 168 169 #if defined(SUPPORT_DSI) 170 extern __u32 dsi_pixel_bits[4]; 171 extern __u32 tcon_div; 172 #endif 173 extern s32 disp_delay_us(u32 us); 174 extern s32 disp_delay_ms(u32 ms); 175 extern int de_get_clk_rate(void); 176 177 #endif 178