1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author        Notes
8  * 2010-11-13     weety     first version
9  */
10 
11 #ifndef __ASM_ARCH_TIME_H
12 #define __ASM_ARCH_TIME_H
13 
14 /* Timer register offsets */
15 #define PID12               0x0
16 #define TIM12               0x10
17 #define TIM34               0x14
18 #define PRD12               0x18
19 #define PRD34               0x1c
20 #define TCR             0x20
21 #define TGCR                0x24
22 #define WDTCR               0x28
23 #define CMP12(n)            (0x60 + ((n) << 2))
24 
25 /* Timer register bitfields */
26 #define ENAMODE12_SHIFT         6
27 #define ENAMODE34_SHIFT         22
28 #define TCR_ENAMODE_DISABLE     0x0
29 #define TCR_ENAMODE_ONESHOT     0x1
30 #define TCR_ENAMODE_PERIODIC        0x2
31 #define TCR_ENAMODE_MASK        0x3
32 
33 #define TGCR_TIMMODE_SHIFT      2
34 #define TGCR_TIMMODE_64BIT_GP       0x0
35 #define TGCR_TIMMODE_32BIT_UNCHAINED    0x1
36 #define TGCR_TIMMODE_64BIT_WDOG     0x2
37 #define TGCR_TIMMODE_32BIT_CHAINED  0x3
38 
39 #define TGCR_TIM12RS_SHIFT      0
40 #define TGCR_TIM34RS_SHIFT      1
41 #define TGCR_RESET          0x0
42 #define TGCR_UNRESET            0x1
43 #define TGCR_RESET_MASK         0x3
44 
45 #define WDTCR_WDEN_SHIFT        14
46 #define WDTCR_WDEN_DISABLE      0x0
47 #define WDTCR_WDEN_ENABLE       0x1
48 #define WDTCR_WDKEY_SHIFT       16
49 #define WDTCR_WDKEY_SEQ0        0xA5C6
50 #define WDTCR_WDKEY_SEQ1        0xDA7E
51 
52 enum {
53     T0_BOT,
54     T0_TOP,
55     T1_BOT,
56     T1_TOP,
57     NUM_TIMERS
58 };
59 
60 #endif /* __ASM_ARCH_TIME_H__ */
61 
62