1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2010-11-13 weety first version 9 */ 10 11 #ifndef __DM36X_H__ 12 #define __DM36X_H__ 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 19 #include <rtthread.h> 20 #include "psc.h" 21 #include "irqs.h" 22 #include "dm365_timer.h" 23 24 /** 25 * @addtogroup DM36X 26 */ 27 /*@{*/ 28 29 /* 30 * Base register addresses 31 */ 32 #define DAVINCI_DMA_3PCC_BASE (0x01C00000) 33 #define DAVINCI_DMA_3PTC0_BASE (0x01C10000) 34 #define DAVINCI_DMA_3PTC1_BASE (0x01C10400) 35 #define DAVINCI_I2C_BASE (0x01C21000) 36 #define DAVINCI_TIMER0_BASE (0x01C21400) 37 #define DAVINCI_TIMER1_BASE (0x01C21800) 38 #define DAVINCI_WDOG_BASE (0x01C21C00) 39 #define DAVINCI_PWM0_BASE (0x01C22000) 40 #define DAVINCI_PWM1_BASE (0x01C22400) 41 #define DAVINCI_PWM2_BASE (0x01C22800) 42 #define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) 43 #define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) 44 #define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) 45 #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) 46 #define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) 47 #define DAVINCI_IEEE1394_BASE (0x01C60000) 48 #define DAVINCI_USB_OTG_BASE (0x01C64000) 49 #define DAVINCI_CFC_ATA_BASE (0x01C66000) 50 #define DAVINCI_SPI_BASE (0x01C66800) 51 #define DAVINCI_GPIO_BASE (0x01C67000) 52 #define DAVINCI_UHPI_BASE (0x01C67800) 53 #define DAVINCI_VPSS_REGS_BASE (0x01C70000) 54 #define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) 55 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) 56 #define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) 57 #define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) 58 #define DAVINCI_IMCOP_BASE (0x01CC0000) 59 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) 60 #define DAVINCI_VLYNQ_BASE (0x01E01000) 61 #define DAVINCI_MCBSP_BASE (0x01E02000) 62 #define DAVINCI_MMC_SD_BASE (0x01E10000) 63 #define DAVINCI_MS_BASE (0x01E20000) 64 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) 65 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) 66 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) 67 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) 68 #define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) 69 70 71 /* 72 * We can have multiple VLYNQ IPs in our system. 73 * Define 'LOW_VLYNQ_CONTROL_BASE' with the VLYNQ 74 * IP having lowest base address. 75 * Define 'HIGH_VLYNQ_CONTROL_BASE' with the VLYNQ 76 * IP having highest base address. 77 * In case of only one VLYNQ IP, define only the 78 * 'LOW_VLYNQ_CONTROL_BASE'. 79 */ 80 #define LOW_VLYNQ_CONTROL_BASE DAVINCI_VLYNQ_BASE 81 82 #define DM365_EMAC_BASE (0x01D07000) 83 #define DM365_EMAC_CNTRL_OFFSET (0x0000) 84 #define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) 85 #define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) 86 #define DM365_EMAC_MDIO_OFFSET (0x4000) 87 #define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) 88 89 90 /* 91 * Macro to access device power control 92 */ 93 #define DAVINCI_VDD3P3V_PWDN (DAVINCI_SYSTEM_MODULE_BASE + 0x48) 94 #define DAVINCI_VSCLKDIS (DAVINCI_SYSTEM_MODULE_BASE + 0x6c) 95 96 /* 97 * System module registers 98 */ 99 #define PINMUX0 (DAVINCI_SYSTEM_MODULE_BASE + 0x00) 100 #define PINMUX1 (DAVINCI_SYSTEM_MODULE_BASE + 0x04) 101 #define PINMUX2 (DAVINCI_SYSTEM_MODULE_BASE + 0x08) 102 #define PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c) 103 #define PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10) 104 105 #define DM365_ARM_INTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x18) 106 #define DM365_EDMA_EVTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x1C) 107 #define DAVINCI_PUPDCTL1 (DAVINCI_SYSTEM_MODULE_BASE + 0x7C) 108 109 110 111 #define ASYNC_EMIF_REVID 0x00 112 #define ASYNC_EMIF_AWCCR 0x04 113 #define ASYNC_EMIF_A1CR 0x10 114 #define ASYNC_EMIF_A2CR 0x14 115 #define ASYNC_EMIF_A3CR 0x18 116 117 /* 118 * Base register addresses common across DM355 and DM365 119 */ 120 #define DM3XX_TIMER2_BASE (0x01C20800) 121 #define DM3XX_REALTIME_BASE (0x01C20C00) 122 #define DM3XX_PWM3_BASE (0x01C22C00) 123 #define DM3XX_SPI_BASE (0x01C66000) 124 #define DM3XX_SPI0_BASE DM3XX_SPI_BASE 125 #define DM3XX_SPI1_BASE (0x01C66800) 126 #define DM3XX_SPI2_BASE (0x01C67800) 127 128 129 130 /* 131 * DM365 base register address 132 */ 133 #define DM365_DMA_3PTC2_BASE (0x01C10800) 134 #define DM365_DMA_3PTC3_BASE (0x01C10C00) 135 #define DM365_TIMER3_BASE (0x01C23800) 136 #define DM365_ADCIF_BASE (0x01C23C00) 137 #define DM365_SPI3_BASE (0x01C68000) 138 #define DM365_SPI4_BASE (0x01C23000) 139 #define DM365_RTC_BASE (0x01C69000) 140 #define DM365_KEYSCAN_BASE (0x01C69400) 141 #define DM365_UHPI_BASE (0x01C69800) 142 #define DM365_IMCOP_BASE (0x01CA0000) 143 #define DM365_MMC_SD1_BASE (0x01D00000) 144 #define DM365_MCBSP_BASE (0x01D02000) 145 #define DM365_UART1_BASE (0x01D06000) 146 #define DM365_EMAC_CNTRL_BASE (0x01D07000) 147 #define DM365_EMAC_WRAP_RAM_BASE (0x01D08000) 148 #define DM365_EMAC_WRAP_CNTRL_BASE (0x01D0A000) 149 #define DM365_EMAC_MDIO_BASE (0x01D0B000) 150 #define DM365_VOICE_CODEC_BASE (0x01D0C000) 151 #define DM365_ASYNC_EMIF_CNTRL_BASE (0x01D10000) 152 #define DM365_MMC_SD0_BASE (0x01D11000) 153 #define DM365_MS_BASE (0x01D20000) 154 #define DM365_KALEIDO_BASE (0x01E00000) 155 156 #define DAVINCI_UART0_BASE (0x01C20000) 157 158 #define PSC_MDCTL_BASE (0x01c41a00) 159 #define PSC_MDSTAT_BASE (0x01c41800) 160 #define PSC_PTCMD (0x01c41120) 161 #define PSC_PTSTAT (0x01c41128) 162 163 #define DM365_EINT_ENABLE0 0x01c48018 164 #define DM365_EINT_ENABLE1 0x01c4801c 165 166 #define davinci_readb(a) (*(volatile unsigned char *)(a)) 167 #define davinci_readw(a) (*(volatile unsigned short *)(a)) 168 #define davinci_readl(a) (*(volatile unsigned int *)(a)) 169 170 #define davinci_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) 171 #define davinci_writew(v,a) (*(volatile unsigned short *)(a) = (v)) 172 #define davinci_writel(v,a) (*(volatile unsigned int *)(a) = (v)) 173 174 #define readb(a) davinci_readb(a) 175 #define readw(a) davinci_readw(a) 176 #define readl(a) davinci_readl(a) 177 178 #define write(v,a) davinci_writeb(v,a) 179 #define writew(v,a) davinci_writew(v,a) 180 #define writel(v,a) davinci_writel(v,a) 181 182 /* define timer register struct*/ 183 typedef struct timer_regs_s { 184 rt_uint32_t pid12; /* 0x0 */ 185 rt_uint32_t emumgt_clksped; /* 0x4 */ 186 rt_uint32_t gpint_en; /* 0x8 */ 187 rt_uint32_t gpdir_dat; /* 0xC */ 188 rt_uint32_t tim12; /* 0x10 */ 189 rt_uint32_t tim34; /* 0x14 */ 190 rt_uint32_t prd12; /* 0x18 */ 191 rt_uint32_t prd34; /* 0x1C */ 192 rt_uint32_t tcr; /* 0x20 */ 193 rt_uint32_t tgcr; /* 0x24 */ 194 rt_uint32_t wdtcr; /* 0x28 */ 195 rt_uint32_t tlgc; /* 0x2C */ 196 rt_uint32_t tlmr; /* 0x30 */ 197 } timer_regs_t; 198 199 /*****************************/ 200 /* CPU Mode */ 201 /*****************************/ 202 #define USERMODE 0x10 203 #define FIQMODE 0x11 204 #define IRQMODE 0x12 205 #define SVCMODE 0x13 206 #define ABORTMODE 0x17 207 #define UNDEFMODE 0x1b 208 #define MODEMASK 0x1f 209 #define NOINT 0xc0 210 211 struct rt_hw_register 212 { 213 rt_uint32_t cpsr; 214 rt_uint32_t r0; 215 rt_uint32_t r1; 216 rt_uint32_t r2; 217 rt_uint32_t r3; 218 rt_uint32_t r4; 219 rt_uint32_t r5; 220 rt_uint32_t r6; 221 rt_uint32_t r7; 222 rt_uint32_t r8; 223 rt_uint32_t r9; 224 rt_uint32_t r10; 225 rt_uint32_t fp; 226 rt_uint32_t ip; 227 rt_uint32_t sp; 228 rt_uint32_t lr; 229 rt_uint32_t pc; 230 }; 231 232 /*@}*/ 233 234 #ifdef __cplusplus 235 } 236 #endif 237 238 #endif 239